[SOLVED] PLL bandwidth bigger or smaller than input frequency?

The PLL transfer function makes it look like a low pass filter.


And everywhere I see, the PLL bandwidth is designed to be 1/10 of the input frequency.

If the BW of the PLL is much lesser than the input frequency doesn't it mean the input frequency will just get filtered out by the PLL?
What am I missing here?

It means the difference frequency is being filtered out.

If you use the XOR gate Type I mixer, the capture range is strongly affected by the BW so lag/lead C-RC filter is used.

YOu can also use dual BW in the loop to change bandwidth from fast lock (high BW) to (low BW) in order to reduce jitter once locked on.

SunnySkyguy said:

It means the difference frequency is being filtered out.

Click to expand...

Ah okay. So the output of the Phase frequency detector should see a low bandwidth? So reduce the noise sent to the VCO

Its more than that.

The loop needs time to slowly adjust and self correct. If you try to do that too fast it will overshoot and nothing you can do will stop it from being unstable.
Its generally accepted that 1/10 to 1/20 is a workable time constant to aim for, and then you can tweak the damping for ideal response.

If you try to correct much faster than that, it will always over correct and be unstable.

Hi,
I had the same confusion before. The input frequency there refers to 'input jitter frequency'. With how much jitter you can track you input voltage(frequency) correctly is determined by how fast is your loop. Remember that the closed loop transfer function is phi_out (s)/phi_in (s) ,the 's' parameter is the rate of change of phase. If you don't have any jitter,the phase increases linearly,ther is no freq component. But when you allow little jitter,the phase will not just be linear. It varies from the ideal waveform. So,the transfer function graph whatever we draw for the CL PLL,the x-axis frequency is the 'FREQUENCY OF THE JITTER'. So, it is a tradeoff b/w speed and noise. The more jitter frequencies you want to track,the more the BW you must choose,the more the noise.
Hope it helps.
Cheers!

If you don't have any jitter,the phase increases linearly,ther is no freq component. But when you allow little jitter,the phase will not just be linear

Click to expand...

1. Hi can you explain that part in detail?

2. My understanding of jitter is that its a very slight shift in the time period for every clock cycle. But you don't want to replicate this error on the output so the B.W has to be as low as possible, but this impacts the lock time. So a trade off must be chosen. Is my understanding correct here?

PLL bandwidth has a great effect of Capture Range, Capture Time, Clock Jitter reduction.

If the signal has a wide dynamic range or large frequency error or marginal SNR, then a simple LPF after the mixer will give too much compromise. So a Lag-lead filter is used, which is simply C1//(C2+R) type feedback filter.

It depends what you want the loop to do.
Small bandwidth and a slow over damped response will definitely reduce output jitter.
That is fine for constant frequency operation.

But if you are repeatedly switching between different frequencies, or if the loop needs to track a varying input frequency, a faster lock time is often a pretty major requirement.

Hi,
If there is no jitter,say the frequency of a periodic signal is constant,that is the phase which is the integral of it increases linearly with time. But once you have jitter, the phase waveform is no longer linear. It may have variations above and below the ideal linear wave form i.e. the frequency of the jitter affects the rate at which the phase changes. (This variation in wave forms are clearly demonstrated in Razavi's book)

Yeah,jitter is that. Now you bandwidth will determine whether you can safely track signals even with jitter. The requirement changes with the application. In some cases,you may want to track and multiply the frequency of the signals with high jitter frequencies,there you would need a high bandwidth and in some cases, you may get a very clean clock from the source and you can do the trick with minimal bandwidth , thereby even attenuating other noise sources.

you may get a very clean clock from the source and you can do the trick with minimal bandwidth

Click to expand...

If the input to my PLL is a very clean clock pulse with almost no jitter, then even if I raise the bandwidth I'm going to draw in any noise. So shouldn't I increase the bandwidth to increase lock time?

amsdesign said:

If the input to my PLL is a very clean clock pulse with almost no jitter, then even if I raise the bandwidth I'm going to draw in any noise. So shouldn't I increase the bandwidth to increase lock time?

Click to expand...

Supply is just one source of noise. Then there is VCO which also produces jitter,which is actually high pass type. It allows jitters of high frequency into the loop,so the poles in the loop must attenuate this error,which again asks you to reduce the bandwidth.
Admist all the trade-offs,we need to select an optimum value for the bandwidth depending on the application.
Please read Razavi from page567.

amsdesign said:

If the input to my PLL is a very clean clock pulse with almost no jitter, then even if I raise the bandwidth I'm going to draw in any noise. So shouldn't I increase the bandwidth to increase lock time?

Click to expand...

You have that backwards. You must increase BW and noise jitter amplification to capture your worst case error frequency, unless using a Type II mixer which has inherent noise from dead-band when rising edges are locked in phase limited by speed of mixer.

Lock time is proportional to loop rise time and error frequency. Even unfilltered error voltage may still be be too small due to control the VCO error frequency to lock ( or capture)

The XOR mixer helps filter noise is also a nonlinear harmonic mixer and does not increase phase error voltage if the signal is off by 1 Hz or 1MHz ( logic level limits are just for phase error) such that the the PLL can lock onto the wrong frequency such as a harmonic of the input signal.

Using an XOR Type I mixer means the phase error voltage is linear but the frequency error is very nonlinear and when out of phase you have a positive feedback loop which pushes the VCO away. So the capture range is limited by the detector charge pump integrator dynamics which must pull harder than push and this difference gets rapidly smaller with error frequency to filter bandwidth ratio, such that it cannot lock on. Thus the filter bandwidth and loop gain must be wider than the worst case error frequency to capture this ac error signal and pull it in 0 phase error.

the Phase Frequency Type II mixer mitigates this error but also amplifies ( essentially dithers around the deadtime inherent to all digital ph/f mixers ) . But this is often necessary if only using an RC VCO and a large frequency error and may be perfectly acceptable for synthesizing a clock where minor jitter is tolerable but not for an RF Tx that multiplies phase noise with divider ratio .

Using a XTAL VCXO allows a smaller error frequency and thus a lower phase noise to capture with a smaller bandwidth.
Using the VCXO to lock onto a Receive signal and hold then allows the Tx synthesized clock to be stable for more tolerant spread-spectrum modulation bursts but yet may not be adequate still for other types of coherent modulation where phase noise must be extremely small for low phase modulation schemes.