Please verify my simple Verilog program

Verilog Program

Can you help me?

I’m currently looking at the following Verilog Example



An FPGA has the following four inputs: Reset, AClk, SigA, and BClk. It has one output, SigB.
Reset is a glitch-free, high-true asynchronous reset.
AClk and BClk come from two different oscillators.
The external circuit that drives SigA does so from an AND gate. The two inputs to that AND gate are driven by flip-flops clocked by AClk.
The sequence of events is as follows:
1) Reset asserts and deasserts asynchronously.
2) Several AClk and BClk cycles elapse.
3) SigA asserts for one AClk cycle and never asserts again.

Your FPGA must assert SigB for one BClk period in response to the asssertion of SigA.

Please provide Verilog code that implements the above design.



Here is what I’ve written:

module example(sigA,Aclk,Bclk,Reset,sigB);

inout sigA;

input wire Aclk;

input wire Bclk;

input wire Reset;

output sigB;

reg sigA;

reg sigB;

reg X;

reg Y;

//reg Z;

always @(posedge Reset)

if ((Aclk==1'b1) && (X==1'b1) && (Y==1'b1))

begin

sigA <= X & Y;

if (Bclk==1'b1)

sigB <=1'b1;

else

sigB <=1'b0;

end

else

sigA<=1'b0;

endmodule



I’ve used two signals called X and Y which are the inputs for the AND gate.

Please let me know incase I’ve made a mistake.