tonnes9
Newbie level 2
hello every1 i am kind of a newbie to vhdl design.how do i design a 4 bit synchronous counter which uses T type flip flop?the counter increments on each positive edge of the clock if enable signal is asserted.
the counter is reset to 0 by using reset signal.
it uses an AND gate,where Tn=Q0Q1.....Qn-1
since its a synch. counter does it matter i use a synchr. reset or asynchr. reset?pls help realy urgent!!!
the counter is reset to 0 by using reset signal.
it uses an AND gate,where Tn=Q0Q1.....Qn-1
since its a synch. counter does it matter i use a synchr. reset or asynchr. reset?pls help realy urgent!!!
Last edited: