Please, help trying to find a design to do that......

[Mr Anderson]

......this is the concept of the operation for the circuit I am loooking for.....I tried to implement the switches with some different PMOS configurations but it didn´t work. I had problems with load level voltages (lower thn i expected) given by the 2 power sources, the battery and the external voltage. Actually the load is the input of a 3.3V regulator voltage chip. Anyone knows any circuit design or chip to obtain the same operation?

 

[Kral]

There are several things to consider:
1
The gate-source voltage magnitude must be greater than the rated Vgs(on) rating of the FET. The amount that you need to exceed the Vgs(on) rating is approximately equal to: DeltaV = Iload/gfs, where gfs is the minimumum rated forward transconductance of the FET. Example:
. Vgs(on) = -2V
. Iload = 10 Amperes
. gfs = 5
Then
. Vgs must be at least -2 - 10/5 = -4V.
2
The saturation current (current where the drain current vs Vgs curve flattens out) must be greater than the maximum load current. Look at the data sheet curves to determine this.
3
Since you are working with positive source and load voltages, it would be easier to design a switching circuit that uses NMOS FETs. That way the Vgs for the "On" state would be positive.
Regards,
Jon

Added after 1 minutes:

There are several things to consider:
1
The gate-source voltage magnitude must be greater than the rated Vgs(on) rating of the FET. The amount that you need to exceed the Vgs(on) rating is approximately equal to: DeltaV = Iload/gfs, where gfs is the minimumum rated forward transconductance of the FET. Example:
. Vgs(on) = -2V
. Iload = 10 Amperes
. gfs = 5
Then
. Vgs must be at least -2 - 10/50 = -4V.
2
The saturation current (current where the drain current vs Vgs flattens out) must be greater than the maximum load current.
.
Since you are working with positive source and load voltages, it might be easier to design a switching circuit that uses NMOS FETs. That way the Vgs would be positive.
Regards,
Jon