Please Help Single Ended Folded Cascode

[Nikhil Motiani]

Task is to design a folded cascode with single ended output[Differential amplifier + common gate stage]
Conditions required are:

Technology TSMC 180nm technology*
VDD 3.3
CL ≥ 500fF
Current mirror ratios ≤ 20
Power Dissipation ≤ 3mW
DC Gain ≥ 80 dB
UGB ≥ 600 MHz
Phase margin ≈ 55 degree
CMRR ≥120dB
PSRR ≥ 100dB

I set up the bias circuit, along with the schematic with all mosfets in saturation. Also i got gain 95dB but the problem is to set the UGB and Phasemargin simultaneously... Please help...

 

[skamthey]

UGB>600MHz is very tough to achieve.
Please specify the pole locations.

 

[kingswan]

Have you done the hand calculation? For your design, to achieve the 600Mhz UGB, the Gm of differential input stage should be at least 300uA/V, so plz check is that Gm1 lower than the 300uA/V. If it does, you can try to increase the bias current to increase the Gm1.