please help me see what error is in the code!!!!

[junchaoguo51888]

why i can't generate the simulate waveform in ISE with HDL bencher?


library IEEE;
use IEEE.STD_LOGIC_1164.all;

package rom_pack is


subtype rom1_word is std_logic_vector( 10 downto 0);
subtype rom_range is integer range 0 to 31;
type rom1_array is array(rom_range) of rom1_word;

function logic2int(din: std_logic_vector(4 downto 0)) return rom_range ;

constant rom1:rom1_array :=(
"00000011001", "00001001011", "00001111101", "00010101111",
"00011100001", "00100010011", "00101000101", "00101110110",
"00110101000", "00111011001", "01000001010", "01000111010",
"01001101010", "01010011010", "01011001001", "01011111000",
"01100100111", "01101010100", "01110000010", "01110101111",
"01111011011", "10000000111", "10000110010", "10001011100",
"10010000110", "10010101111", "10011011000", "10011111111",
"10100100110", "10101001100", "10101110001", "10110010110"
);



end rom_pack;

package body rom_pack is
function logic2int(din: std_logic_vector(4 downto 0)) return rom_range is
variable result :rom_range :=0;
begin
for i in 0 to 4 loop
if din(i)='1' then
result:=result+2**i;
end if ;
end loop;
return result;
end function logic2int;

end rom_pack;







library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.rom_pack.all;

entity rom_logic is
Port ( aaddr: in std_logic_vector(4 downto 0);
read: in std_logic;
sinaout : out std_logic_vector(10 downto 0)
);
end rom_logic;

architecture Beh of rom_logic is
begin
process(read)
begin

if (read='1') then
sinaout<=rom1(logic2int(aaddr));

else
sinaout<=(others=>'Z');

end if;

end process;


end Beh;

 

[junchaoguo51888]

the report error is :error(s) where encountered while extracting ports ,please check the syntax of rom_logic,but when i check it ,it has no error,

 

[maestor]

Hi junchaoguo51888,

The code looks ok to me...I have just compile your files with Models!m and then loaded the top module and doesn't complain.

Did you find the problem already...? if not maybe you could post more details...

Regards,

-Maestor

 

[r_e_m_y]

Hi,

try this :

sinaout<=rom1(conv_integer(aaddr));

instead of your logic2int custom function