Please help me: about SOC test

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I am assigned to design a small SOC chip. There are cpu, memory and some digital/anolog modules are used in it. About test, the desire is:
(1) The least test pins are used.
(2) The least test time.
(3) The smallest area of test circuit.

Please help me to find a good solution. Thanks.
 


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Hi,

From your question it is not easy for me to help you, can you please specify is it ASIC or FPGA design, and what is the functionality of your design and more details.


To achieve your (2) and (3) goals you can implement faster system clock and small-size technology(0.18u-0.13u).

Regards,
 

BIST for Memory test.

Scan for other modules.
 

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