Please help: Issue opening a text file through verilog/SV code in Modelsim simulator

***********Error code is as follows:*************

** Warning: (vsim-3534) [FOFIR] - Failed to open file "switch.txt" for reading.
#
# No such file or directory. (errno = ENOENT) : C:/Modeltech_pe_edu_10.1d/examples/SystemVerilogPractice/associativeArray.sv(51)
# Time: 0 ps Iteration: 0 Instance: /associativeArry
# error in opening the file

****************Code excerpt is as follows:******

initial
begin : initial_block2
int i, r, file; // 32 bit values
string s;

// opening a file
file = $fopen ("switch.txt", "r");

if (file == 0)
begin
$display ("error in opening the file");
end
else
begin
$display ("success in opening the file");
end
end :initial_block2

****** Version details*************************
ModelSim PE student edition 10.1d

*** I have already tried the following things************************

1. Added the path Using: File>Source Directory
2. Added the path Using: Compiler options> Verilog & systemVerilog > Include Directroy
3. The file"Switch.txt" is in the work directory as well as in the project directory "SystemVerilogPractice"

Does this file exist before you start the simulation. Note simulation will not create this file as you have opened it in read-only mode. You must create the file manually and then run the simulation.

tariq786 said:

Does this file exist before you start the simulation. Note simulation will not create this file as you have opened it in read-only mode. You must create the file manually and then run the simulation.

Click to expand...

Yes, I have created the file "switch.txt" and it is available in the paths i mentioned in my above message. Still I have the same problem. I have had this problem with opening a memory file as well..... I Just do not know how to fix this one

Use only one initial block. Secondly does ModelSim 10.1d PE support system verilog?

Source and include file paths are only for compilation and have no effect on $fopen.

As an experiment, you could try opening a new file for writing and see where it puts it.

As a lst resort, try giving the full path "C:/Modeltech_pe_edu_10.1d/examples/SystemVerilogPractice/switch.txt"

And yes, all versions of ModelSim support SystemVerilog except certain testbench features like assertions, covergroups, and randomize().

tariq786 said:

Use only one initial block. Secondly does ModelSim 10.1d PE support system verilog?

Click to expand...

Hi tariq786... How is using only one initial block will help. I can not understand the logic behind your suggestion. Please elaborate
As as Dave said, ModelSim 10.1d does supports systemverilog.

Regards
Avinash

- - - Updated - - -

dave_59 said:

Source and include file paths are only for compilation and have no effect on $fopen.

As an experiment, you could try opening a new file for writing and see where it puts it.

As a lst resort, try giving the full path "C:/Modeltech_pe_edu_10.1d/examples/SystemVerilogPractice/switch.txt"

And yes, all versions of ModelSim support SystemVerilog except certain testbench features like assertions, covergroups, and randomize().

Click to expand...

Hi Dave,

Thanks you very much for your help. when I created the file through the code, reading it back actually worked. I was able to figure out the path where it was created.

However, the suggestion that you gave as lst resort still did not work. I do not know why? ( I Kept "\" operator in mind and tried putting single slash as well as double slash.)

Thanks for your help, I can now play around more.

Regards
Avinash

However, the suggestion that you gave as lst resort still did not work. I do not know why? ( I Kept "\" operator in mind and tried putting single slash as well as double slash.)

Click to expand...

ap,

Make all the path delimiters / (forward slashes). I've found that using \ is much more likely to have issues with finding the file.