please help i am a beginner and its really confusing me.

hi i tried to simulate this code in Quartus simulation tool but the counter is giving me characters. i cant figure out what is wrong. please help.



LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
--
--use work.SinglePortRAM_pack.all;

ENTITY test5 IS
PORT(
clk : IN std_logic;
-- Pb0a : IN std_logic;
Pb1a : IN std_logic;
-- led0a : OUT std_logic;
-- led1a: out std_logic;
-- led2a: out std_logic;
-- led3a: out std_logic;
-- led4a: out std_logic;
-- led5a: out std_logic;
-- led6a: out std_logic;
-- led7a: out std_logic ;
-- dac_outputut std_logic_vector(7 downto 0)
sine_outputut std_logic_vector(7 downto 0)
);

END test5 ;


ARCHITECTURE led OF test5 IS
--type byte is std_logic_vector ( 7 downto 0);
--signal cnt: std_logic_vector(2 downto 0) := "001";
--signal dac_cnt_1: std_logic_vector(7 downto 0) := "00000000";
--signal edge_sig: std_logic_vector(1 downto 0) := (others => '1');
--signal cnt2: std_logic_vector(23 downto 0) := (others => '0');
--signal level1,level2,level3: std_logic;
signal n_reset : std_logic ;

--signal LUT : array ( 0 to 256) of byte;
--type state is Q1, Q2, Q3, Q4) ; -- of std_logic_vector(7 downto 0);
type STATE_TYPE is (Q1, Q2, Q3, Q4);
signal current_state : STATE_TYPE;

type table is array (0 to 127) of std_logic_vector(7 downto 0);

signal dac_cnt: natural range 0 to 256 ; --integer
signal LUT : table :=

(
0 => "00000000",
1 => "00000010",
2 => "00000011",
3 => "00000101",
4 => "00000110",
5 => "00001000",
6 => "00001001",
7 => "00001011",
8 => "00001100",
9 => "00001110",
10 => "00010000",
11 => "00010001",
12 => "00010011",
13 => "00010100",
14 => "00010110",
15 => "00010111",
16 => "00011001",
17 => "00011010",
18 => "00011100",
19 => "00011101",
20 => "00011111",
21 => "00100000",
22 => "00100010",
23 => "00100011",
24 => "00100101",
25 => "00100110",
26 => "00101000",
27 => "00101001",
28 => "00101011",
29 => "00101100",
30 => "00101110",
31 => "00101111",
32 => "00110001",
33 => "00110010",
34 => "00110011",
35 => "00110101",
36 => "00110110",
37 => "00111000",
38 => "00111001",
39 => "00111010",
40 => "00111100",
41 => "00111101",
42 => "00111111",
43 => "01000000",
44 => "01000001",
45 => "01000011",
46 => "01000100",
47 => "01000101",
48 => "01000111",
49 => "01001000",
50 => "01001001",
51 => "01001010",
52 => "01001100",
53 => "01001101",
54 => "01001110",
55 => "01001111",
56 => "01010001",
57 => "01010010",
58 => "01010011",
59 => "01010100",
60 => "01010101",
61 => "01010110",
62 => "01011000",
63 => "01011001",
64 => "01011010",
65 => "01011011",
66 => "01011100",
67 => "01011101",
68 => "01011110",
69 => "01011111",
70 => "01100000",
71 => "01100001",
72 => "01100010",
73 => "01100011",
74 => "01100100",
75 => "01100101",
76 => "01100110",
77 => "01100111",
78 => "01101000",
79 => "01101001",
80 => "01101010",
81 => "01101010",
82 => "01101011",
83 => "01101100",
84 => "01101101",
85 => "01101110",
86 => "01101111",
87 => "01101111",
88 => "01110000",
89 => "01110001",
90 => "01110001",
91 => "01110010",
92 => "01110011",
93 => "01110011",
94 => "01110100",
95 => "01110101",
96 => "01110101",
97 => "01110110",
98 => "01110110",
99 => "01110111",
100 => "01111000",
101 => "01111000",
102 => "01111001",
103 => "01111001",
104 => "01111010",
105 => "01111010",
106 => "01111010",
107 => "01111011",
108 => "01111011",
109 => "01111100",
110 => "01111100",
111 => "01111100",
112 => "01111101",
113 => "01111101",
114 => "01111101",
115 => "01111101",
116 => "01111110",
117 => "01111110",
118 => "01111110",
119 => "01111110",
120 => "01111110",
121 => "01111111",
122 => "01111111",
123 => "01111111",
124 => "01111111",
125 => "01111111",
126 => "01111111",
127 => "01111111"
);
--signal current_state, next_state: state;

BEGIN
n_reset <= Pb1a;

process(clk,n_reset)
begin
--dac_cnt <= conv_integer(unsigned( dac_cnt_1));
--if n_reset = '0' then
-- dac_cnt <= 0; --<= (others => '0');--:= 0;
-- current_state <= Q1;



--CONV_integer(unsigned(dac_cnt(7 downto 0))) <= CONV_integer(unsigned(dac_cnt(7 downto 0)))+ '1';--:= dac_cnt + 1;

--elsif rising_edge(clk) then
if rising_edge(clk) then
if n_reset = '0' then
dac_cnt <= 0 ; --(others => '0'); --0; --<= (others => '0');--:= 0;
current_state <= Q1;

else

case current_state is
when Q1 => -- vec1 <= std_logic_vector(conv_unsigned((int1),8 ))
dac_cnt <= dac_cnt + 1; --<= dac_cnt + '1' ; -- <= dac_cnt + '1';
-- dac_cnt <= conv_integer(unsigned( dac_cnt_1));
sine_output <= "10000000" + LUT(dac_cnt);
--sine_output <= "10000000" + LUT( CONV_integer(unsigned(dac_cnt(7 downto 0))) );
-- cnt2 <= cnt2 + '1';
--if MSB of dac_cnt = '1' then
if dac_cnt = 127 then
current_state <= Q2;
end if;

when Q2 =>
dac_cnt <= dac_cnt - 1 ;
--dac_cnt <= dac_cnt - '1' ;--<= dac_cnt + '1'; --
sine_output<= "10000000" + LUT(dac_cnt);
-- cnt2 <= cnt2 - '1';
if dac_cnt = 0 then
current_state <= Q3;
end if;

when Q3 =>
dac_cnt <= dac_cnt + 1; --<= dac_cnt + '1';--
sine_output<= "10000000" - LUT(dac_cnt);
-- cnt2 <= cnt2 + '1';
--if MSB of dac_cnt = '0' then
if dac_cnt = 127 then
current_state <= Q4;
end if;

when Q4 =>
dac_cnt <= dac_cnt - 1; --<= dac_cnt + '1';--
sine_output <= "10000000" - LUT(dac_cnt);
-- cnt2 <= cnt2 - '1';
if dac_cnt = 0 then
current_state <= Q1;
end if;

when others =>
current_state <= Q1;
end case;
end if;
end if;
end process;
END ARCHITECTURE led;

i am trying to generate a quarter wave and play it back as a full one.

Remove the commented lines or use the "code" block to display your code.This way it is very difficult to understand what you have done.

--vipin
https://vhdlguru.blogspot.com/

but the counter is giving me characters

Click to expand...

You're talking in riddles.