onion2014
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i read the protocol 3 times and I think i understand it.
Based on the protocol, the address decoder is combinational logic. its inputs are just the address from the master, so its outputs are in the same cycle with the address cycle. But ahb's data cycle is one cycle after the addr cycle. So in the figure, at some point between T5 and T6, the read data mux already choose the new slave selected by the new master. So in T7, the previous master can not sample the correct.
One possible solution i can think of is that the read data mux is controlled by the arbiter rather than the decoder. the addr decoder just control the Hselx. I think of this because I see a HADDR signal working as inputs to the arbiter.