[SOLVED] Please Help Bugs in verilog code State Machine In Active HDl ?

[blooz]

Hai the the code is as follows it compiles without error but the Waveforms when Simulated Doesnot match with Requirement .I Intended to design a mode 4 Counter but the simulation does take place but with wrong result

//Code mode 4 counter in verilog



//-----------------------------------------------------------------------------
//
// Title : No Title
// Design : verilog_systemc_parameters
// Author : Neural
// Company : Artificial_Resonance
//
//-----------------------------------------------------------------------------
//
// File : F:\My_Designs\Samples_72\verilog_systemc_parameters\compile\a1.v
// Generated : 01/23/11 13:13:12
// From : F:\My_Designs\Samples_72\verilog_systemc_parameters\src\a1.asf
// By : FSM2VHDL ver. 5.0.3.4
//
//-----------------------------------------------------------------------------
//
// Description :
//
//-----------------------------------------------------------------------------

`timescale 1ns / 1ps

module a1 (clk, out, reset);
input clk;
input reset;
output [1:0] out;

wire clk;
reg [1:0] out, next_out;
wire reset;

// BINARY ENCODED state machine: Sreg0
// State codes definitions:
`define S1 2'b00
`define S2 2'b01
`define S3 2'b10
`define S4 2'b11

reg [1:0] CurrState_Sreg0;
reg [1:0] NextState_Sreg0;


//--------------------------------------------------------------------
// Machine: Sreg0
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (out or CurrState_Sreg0)
begin : Sreg0_NextState
NextState_Sreg0 <= CurrState_Sreg0;
// Set default values for outputs and signals
next_out = out;
case (CurrState_Sreg0) // synopsys parallel_case full_case
`S1:
if (clk)
begin
NextState_Sreg0 <= `S2;
next_out = 2'b01;
end
else
begin
NextState_Sreg0 <= `S1;
next_out = 2'b00;
end
`S2:
if (clk)
begin
NextState_Sreg0 <= `S3;
next_out = 2'b10;
end
else
begin
NextState_Sreg0 <= `S1;
next_out = 2'b00;
end
`S3:
if (clk)
begin
NextState_Sreg0 <= `S4;
next_out = 2'b11;
end
else
begin
NextState_Sreg0 <= `S1;
next_out = 2'b00;
end
`S4:
if (clk)
begin
NextState_Sreg0 <= `S1;
next_out = 2'b00;
end
else
begin
NextState_Sreg0 <= `S1;
next_out = 2'b00;
end
default:
begin
// trap state
NextState_Sreg0 <= `S1;
next_out = 2'b00;
end
endcase
end

//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk or posedge reset)
begin : Sreg0_CurrentState
if (reset==1'b1)
CurrState_Sreg0 <= `S1;
else
CurrState_Sreg0 <= NextState_Sreg0;
end

//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk or posedge reset)
begin : Sreg0_RegOutput
if (reset==1'b1)
begin
out <= 2'b00;
end
else
begin
out <= next_out;
end
end

endmodule

.....

 

[lostinxlation]

always @ ([B][SIZE="4"]out or CurrState_Sreg0[/SIZE][/B])
begin : Sreg0_NextState
	[B][SIZE="4"]NextState_Sreg0 <= CurrState_Sreg0[/SIZE][/B];
	// Set default values for outputs and signals
	next_out = out;
	case (CurrState_Sreg0) // synopsys parallel_case full_case
	
              ..................
	
             endcase
end

//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk or posedge reset)
begin : Sreg0_CurrentState
	if (reset==1'b1)	
		CurrState_Sreg0 <= `S1;
	else
		[B][SIZE="4"]CurrState_Sreg0 <= NextState_Sreg0[/SIZE][/B];
end

I didn't thoroughly look into the code, but ..

The execution of the case statement depends on the change on out or CurrState_Sreg0, and out and CurrState_Sreg0 depend on the execution of the case statement, don't it ?
It seems a deadlock situation to me.

I guess what's missing is always @(out or CurrState... or clk), though I don't think it's a good logic using clk directly in the comb logic.

And...why are you using non-blocking statements in case statement ?

 

[blooz]

I have Changed the code and Now it Works with out any problem ....But I think the code style Adopted seems poor ....
Can you help me Code in a better Style....

the corrected coded is as follows

//


/-----------------------------------------------------------------------------
//
// Title : No Title
// Design : verilog_systemc_parameters
// Author : Neural
// Company : Artificial_Resonance
//
//-----------------------------------------------------------------------------
//
// File : F:\My_Designs\Samples_72\verilog_systemc_parameters\compile\a1.v
// Generated : 01/23/11 14:53:33
// From : F:\My_Designs\Samples_72\verilog_systemc_parameters\src\a1.asf
// By : FSM2VHDL ver. 5.0.3.4
//
//-----------------------------------------------------------------------------
//
// Description :
//
//-----------------------------------------------------------------------------

`timescale 1ns / 1ps

module a1 (clk, out, reset);
input clk;
input reset;
output [1:0] out;

wire clk;
reg [1:0] out, next_out;
wire reset;

// BINARY ENCODED state machine: Sreg0
// State codes definitions:
`define S1 2'b00
`define S2 2'b01
`define S3 2'b10
`define S4 2'b11

reg [1:0] CurrState_Sreg0=2'b00;
reg [1:0] NextState_Sreg0;


//--------------------------------------------------------------------
// Machine: Sreg0
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ ( clk or reset )
if(reset==1'b1)
begin
NextState_Sreg0<= `S1;
out=2'b00;
end
else

begin
case (CurrState_Sreg0) // synopsys parallel_case full_case
`S1:
if (clk)
begin
NextState_Sreg0 <= `S2;
out=2'b01;
end

`S2:
if (clk)
begin
NextState_Sreg0 <= `S3;
out=2'b10;
end

`S3:
if (clk)
begin
NextState_Sreg0 <= `S4;
out=2'b11;
end

`S4:
if (clk)
begin
NextState_Sreg0 <= `S1;
out=2'b00;
end

default:
begin
// trap state
NextState_Sreg0 <= `S1;
out=2'b00;
end
endcase
end

//----------------------------------
// Current State Logic
//----------------------------------
always @ (NextState_Sreg0 or clk)
CurrState_Sreg0 <= NextState_Sreg0;

endmodule

 

[qian15]

Is this you want?

module statetest (clk, out, reset);
input clk;
input reset;
output [1:0] out;

wire clk;
reg [1:0] out, next_out;
wire reset;


`define S1 2'b00
`define S2 2'b01
`define S3 2'b10
`define S4 2'b11

reg [1:0] State_reg;
reg [1:0] State_next;



always @ (posedge clk or negedge reset )
if(!reset)

State_reg<= `S1;

else
State_reg<= State_next;

always @ *
begin
State_next= State_reg;
out=2'b00;
case (State_reg)
`S1:
begin
State_next = `S2;
out=2'b01;
end
`S2:
begin
State_next= `S3;
out=2'b10;
end

`S3:

begin
State_next= `S4;
out=2'b11;
end

`S4:

begin
State_next= `S1;
out=2'b00;
end

default:
begin

State_next= `S1;
out=2'b00;
end
endcase
end




endmodule

 

[YanivS]

`timescale 1ns / 1ps

module a1 (
input
clk,
reset,
output reg [1:0]
out
);


//--------------------------------------------------------------------
// Machine: Sreg0
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (posedge clk or posedge reset )
if(reset)
begin
out <=2'b00;
end
else
begin case(out)
2'b00:
out <= 2'b01;
2'b01:
out <= 2'b10;
2'b10:
out <= 2'b11;
2'b11:
out <= 2'b00;
end

endmodule