Please critique my Buck converter layout (simple LM2596)

Please critique my Buck converter layout (simple LM2596)

Should I pour the entire bottom layer as ground and tie bottom to top layer ground with multiple vias, or split the bottom layer for best results?

Thanks you for you comments.

Are 2 cheap caps better than 1 good Cap with low ESR? Maybe but not if they have the same failure mode from high ESR.

Strategic Copper pour reduce EMI, balance copper layers and reduce thermal resistance is always good.

Did you evaluate the evaluation kit design layout & BOM?

The LM2576 data sheet example circuit has a 100 µF input capacitor, I think for a good reason.

The input current of a buck converter is pulsating by nature, if you operate it from a voltage source with some output impedance, you get respective input voltage ripple. The 10 µF in your circuit are probably sufficient to limit conducted noise in a pure digital system, but the 50 kHz AC current is mainly passed to the primary voltage source.

SunnySkyguy said:

Are 2 cheap caps better than 1 good Cap with low ESR? Maybe but not if they have the same failure mode from high ESR.

Strategic Copper pour reduce EMI, balance copper layers and reduce thermal resistance is always good.

Did you evaluate the evaluation kit design layout & BOM?

Click to expand...

The reference design uses a TO-220, I'm using D2PAK and my PCB shape is different, I have modified to be closer to the reference design, comments please.

The "cheap" caps are not so cheap:
+ Inputs are ceramic
+ Outputs are T491 series Tantalum

Trying to avoid electrolytic for long life.

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FvM said:

The LM2576 data sheet example circuit has a 100 µF input capacitor, I think for a good reason.

The input current of a buck converter is pulsating by nature, if you operate it from a voltage source with some output impedance, you get respective input voltage ripple. The 10 µF in your circuit are probably sufficient to limit conducted noise in a pure digital system, but the 50 kHz AC current is mainly passed to the primary voltage source.

Click to expand...

I used TI's online optimizer software and it reduced the input capacitor to the capacitors shown GRM31CR71H475KA12L

I used TI's online optimizer software and it reduced the input capacitor to the capacitors shown GRM31CR71H475KA12L

Click to expand...

I wrongly assumed 50 kHz switching frequency but LM2596 is 150 kHz. The problem of input current ripple still exists. Obviously ceramic capacitors have no problem to stand the AC current, but it's stil bad design to send the ripple current back to the input source.

I wonder what are the "optimization" criteria of the TI tool.

FvM said:

I wrongly assumed 50 kHz switching frequency but LM2596 is 150 kHz. The problem of input current ripple still exists. Obviously ceramic capacitors have no problem to stand the AC current, but it's stil bad design to send the ripple current back to the input source.

I wonder what are the "optimization" criteria of the TI tool.

Click to expand...

Optimization was set to mid scale (lowest BOM cost vs. Highest efficiency)

I appreciate your comments and will measure ripple with actual power supply that will be used.

Any comments on the proposed layout (post #4)?

I will not trust online tools for optimization...Only basic component calculation and any compensation components calculation ( purely based on personal experience) will be best calculated by online tools ....Human intelligence is required and mandatory......Try to calculate the worst case current(Ripple and peak - mainly transient current) requirement from design. Most of the time during ON time of converter if there is a transient, Input capacitor should give that charge(based on efficiency of the layout) because controller loop bandwidth will not be fast to respond.....