Please check fsm more logic program is correct?

[harerama]

Hi...I written VHDL code for fsm more logic.for sequence 1011,state diagram contain below .please check below behav and test bench programs are correct?


library ieee;
use ieee.std_logic_1164.all;

entity more is
port (input,reset : in std_logic;
clk : in std_logic;
output : out std_logic
);
end more;
architecture test of more is
type state is(s0,s1,s2,s3,s4);
signal m_state : state;
begin
process(clk,reset)
begin
if(reset ='1') then
m_state <= s0;
elsif(rising_edge(clk)) then
case m_state is
when s0 =>
if (input ='1')then
m_state <= s1;
else
m_state <= s0;
end if;

when s1 =>
if(input ='0')then
m_state <= s2;
else
m_state <= s1;
end if;

when s2 =>
if(input='1') then
m_state <= s3;
else
m_state <= s0;
end if;

when s3 =>
if(input ='1') then
m_state <= s4;
else
m_state <=s2;
end if;

when s4 =>
if(input ='0') then
m_state <= s2;
else
m_state <=s1;
end if;
end case;
end if;
end process;
output <= '0' when m_state =s4 else '1';
end;
(test bench)
library ieee;
use ieee.std_logic_1164.all;

entity more_tb is
end more_tb;

architecture test of more_tb is
signal input,reset,clk:std_logic;
signal output : std_logic;
constant clk_period : time := 10 ns;

begin
uut: entity work.more port map(input=>input,reset=>reset,clk=>clk,output=>output);
process
begin
clk <= '0';
wait for clk_period/2;
clk <='1';
wait for clk_period/2;
end process;
process
begin
wait for clk_period;
input <='1';
wait for clk_period;
input <= '0';
wait for clk_period;
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
input <= '1';
wait for clk_period;
input <= '0';
wait for clk_period;
input <= '0';
wait for clk_period;
input <='1';
wait;
end process;
end;

 

[TrickyDicky]

cant you do your own debugging?

 

[harerama]

Thanks for your comments.Little bit doubt its correct or not so i posted..

 

[TrickyDicky]

best thing to do is run it yourself in a simulator, and come back here with specific problems.

 

[harerama]

i ran simulator ,got waveform also..problem is i cant predict.below i attached screen shot.

 

[TrickyDicky]

I suggest adding a reset to your testbench.