Planar transformers for Pushpull 300W 24VIN 32Vout, 250kHz

Synch rect fet's, even if you turn them off all the time - still have the diode that passes current in the required direction.

Thus it is only when this internal diode is commutated off by the volts reversing on the transformer that you can get an over voltage spike - for this reason some designers try to keep the time difference to a minimum - i.e. turn off the synch rect fets as close to zero current as possible - so that the intrinsic diode is not involved too much.

Obviously having resonant transitions on the Tx helps here as the dv/dt on the sec is then much less which helps with any Vrev spikes on the o/p rectifier

hard switched push pulls do not usually have such transistions - even the overlapped choke input variety - so you are stuck with snubbers on the rectifiers ... or an active cap clamp ckt.

Thus it is only when this internal diode is commutated off by the volts reversing on the transformer that you can get an over voltage spike

Click to expand...

...I dare say you yourself have sync rect control algorithms that achieve this. However, i find the standard offtheshelf sync rect drivers leave one open to overvoltage spikes due to the SMPS going into light load suddenly......and then the output inductor current reversing and going the "wrong way" back through the sync rect FET....then the sync rect FET turns off...and the output inductor current has been suddenly broken (and now has nowhere to go)....and thus an overvoltage spike results.....the attached LTspice simulation shows the situation happening at the 2ms point.
(if you change it and make the 1e20R resistors equal to 0.1R (or less), then the effect is mitigated.)


The extra “mitigation circuitry” is not usually tolerated by most project managers….because they say that the offtheshelf solutions must work…otherwise they wouldnt be on the market……but the offthe shelf ones only detect current reversing through the sync rect fet after its started happening…..which is too late really. The offtheshelfer’s also usually detect current reversing through the sync rect fet by “Looking” at the voltage across the rds(on) of the sync rect fet……and AYK this is not a fixed voltage because of rds(on) variation with temperature.

So really, chunky TVS's end up being needed across sync rect fets......or even RCD Clamps.

Most offtheshelf sync rect fet controllers are pretty dreadful things…..and many of them (their datasheets) are honest enough to say how bad the situation of detecting reverse current through the sync rect is…and offer you a way to mitigate noise here by putting in your own compensatory "stray" inductor, to mitigate the effect of stray inductance of eg the TO220 legs, etc.

Here is the NCP4303 sync rect controller

.....it shows the "compensatory inductor" that is needed.
It obviosuly has to be "tuned" in value to your PCB layout "strays" etc.
_____----_____
Also, the Current doubler rectifier, with its two output inductors, and single txformer secondary, is the best topology by far for sync rects, because even if the sync rect fet turns off whilst conducting reverse current, there is still some path for the output inductor current to go.

yes - we do not tolerate any reverse current in the fet.

I note the additional inductor required - it is quite small and could easily be a pcb trace.

leakage inductance in the main Tx and pcb traces make any turn off event in the output rectifers worse - reducing leakage and wiring L should be a designers prime concern.

Actually to this end we did once design/build a pcb multi layer planar Tx, at request of local university, with 4uH Lp, and about 800pH total leakage - it was quite hard to measure and we had to subtract the inductance introduced by the wire shorting the secondary.

On the flip side - some leakage inductance does limit the rate of di/dt in the sec loop - so there is a trade off between this and leakage spikes ....

p.p.s. if the mosfet is gated on too long not only does the output cap discharge into it - but the pri side can do this also ....

Thanks,
With Sync Rect drivers like LTC3901

...What they need is to be accompanied by a simple analog circuit which signals whenever the output loading has been greater than say 30% for 2 seconds......the "signal" should then enable the sync rects and keep them enabled......then, as soon as the loading goes below 30%, the sync rects should be disabled again......this would ensure no reversing current in the sync rects.
This circuit would, i think, best take the form of some kind of opamp integrator "looking" at a current sense resistor...or hi-side current monitor output....as an integrator, it could instigate the "signal" after the two seconds delay.
Anybody got any nice low component count versions of this?

p.p.s. - unless you really know what you are doing - 250kHz is a bad idea - for a plethora of reasons

50-70kHz would be a far safer starting point.

Thanks..... for a pushpull transformer, we have the following Planar transformer spec. (attached).
It gives pri:sec leakage as 1.2uH...but over the phone they have said its actually 0.1uH.
But would you say it was being pinickity to ask for leakage inductance measurement between the one primary half and the other?......ditto leakage inductance between the two secondary halves.

...or is it just taken as wrote that they will have designed it for vanishingly small leakage inductance between one primary half of the pushpull and the other?

Pushpull is 24vin 32vout 300w 225khz, split sec

You don't know until you have one in your hand and test it. You can assume the total leakage as measured will split 50/50 with due regard to turns ratio, measured across the OUTSIDE of the 2 wdgs on the pri side - with all sec's shorted.

Say you get 4uH total and the turns is (2+2) : (4+4), thus you get 2uH on the pri and 8uH on the sec.

This is now 1uH associated with each pri wdg and 4uH associated with each sec wdg

you can check this by shorting one pri and measuring the Llk on the remaining ( it should be 2uH in the above example )

similarly for the sec's

happy measuring ....

A further note - 250kHz on the IC timing cap = 125kHz on the mosfets. So it is a 125kHz converter - NOT 250kHz.

So the transformer DOES NOT match the sw freq given by the 270pF cap on the IC ( = 250kHz clock = 125kHz mosfets = 125kHz transformer ) so the design may be doomed from the start ....

o the transformer DOES NOT match the sw freq given by the 270pF cap on the IC ( = 250kHz clock = 125kHz mosfets = 125kHz transformer ) so the design may be doomed from the start ....

Click to expand...

Thanks, thats a very good point, i will ask them how they define frequency.
I always think of an LLC.....the App Notes always call a 100kHz LLC..., one where each FET actually switch's at 50kHz.

the sw freq is defined by that which the transformer sees - which is the same as the driving H bridge.

So the transformer DOES NOT match the sw freq given by the 270pF cap on the IC ( = 250kHz clock = 125kHz mosfets = 125kHz transformer ) so the design may be doomed from the start ....

Click to expand...

Thanks, do you think the following cheap LCR meter will be ok to measure the leakage inductances of this transformer?

It says that resolution is 0.2uH...but then says accuracy is only 1.5% +/-0.6uH.

...to be honest, +/-0.6uH would be fine......not great , but better than nothing for this price.
A proper LCR meter, AYK, is going to beat us out for £1k or so......no can do.

Also, its datasheet doesnt say if the inductance can be measured at their "offered" measurement frequency of 200kHz....do you know if it is , may i ask?

In an 100kHz LLC I think you will find each fet switches on and off 100,000 times per second.

That LCR meter you show should be OK - resolution has a far different meaning than accuracy.

all you need for an accurate L measurement is a sign gen, scope and resistor, and a set of high Q caps to form a parallel res with the L to be measured.

For example, if the Llk is ~ 1.2uH, to resonate at 125kHz, you need a 1.2nF ( or 1.5nF ) 100V cap

Put in parallel, use a 2k7 resistor to drive this parallel combo from the sig gen - sine - flat out - start near 125kHz

Look at the sig gen out and the parallel LC on the scope - adj freq until the 2 waveforms are in phase - this can be a lil bit tricky ...

then (2. pi. freq)^2 = 1 / ( L . C ), so L is easily got, answer is as accurate as the cap and the sig gen / freq measuring device ....

for a more accurate assesment of L, or Llk, use larger capacitance caps for a lower frequency - this will diminish the effect of the wdg capacitance and the scope probe capacitance

cupoftea said:

I always think of an LLC.....the App Notes always call a 100kHz LLC..., one where each FET actually switch's at 50kHz.

Click to expand...

No.

Thanks, yes youre right, premature senility in my case.
Also, we have a Planar transformer.....the spec is as attached (from the manuf)....it says ER32 core......and inductance of the 4 primary turns is 28.6uH. That gives an AL value of 7150.

But that doesnt correspond to an ER32 core ...

TDK ER32 core...

Woops, sorry, need to delete post....its obviously a ferroxcube core

Please give examples of App Notes of Hard switched Push Pulls with planars?


As a side note....
..........I have been fixing up a bog standard couple of hard switched converters for a customer.

Its bare basic , “electrician level” electronics, but tomorrow, I am being taken to their customer, to answer questions about “giving away secrets”…in relation to these bog standard hard switched converters.

I have never given away real secrets about anything……and these circuits that I have been working on are literally electrician level SMPS designs……the sort of thing you get demo boards on for a couple of quid. The sort of thing that App notes talk about in droves.

They are the sorts of SMPS that a 14 year old could design. It’s the simplest level of electronics….no more secret than an electricians knowledge.

It’s the knowledge of SMPS, that got outsourced to the Pacific Rim years ago…….as if there are secrets in this?.....secrets no way. If it was secret, why all SMPS work is outsourced to the Pacific Rim? They blame people like me for the fact that China is a million miles ahead of the west in SMPS design.

Has anybody else ever been to one of these inquests? What happens?

So, It’s the knowledge of SMPS, that got outsourced to the Pacific Rim years ago…….as if there are secrets in this?.....secrets no way. If it was secret, why all SMPS work is outsourced to the Pacific Rim? They blame people like me for the fact that China is a million miles ahead of the west in SMPS design. Its the west's own fault...for outsourcing massive amounts of SMPS work to the Far East.

AL value = 28.6uH / ( 4T )^2 = AL = 1787nH / T^2

ER32 core has AL = 3800 nH / T^2 so there may be a small gap ? or the material is 3F4 ... ?

UPDATE, based on 2T pri ( which it is ) AL is really 7150, more in line with a good grade of ferrite e.g. 3F3 = 7160

cupoftea said:

I am being taken to their customer, to answer questions about “giving away secrets”…

Has anybody else ever been to one of these inquests?

Click to expand...

Not that I know anything but by putting a spotlight on you, it smells like they'll try to maneuver you into saying something they can turn into an accusation.

Is the project failing? Do they think you'll (knowingly or unknowingly) supply them with details to bring success? At no additional cost? Because you feel apologetic?

Are they looking for a scapegoat? Someone they can sue for any made-up reason?

Take along documents to show them you're not a secret agent or somesuch.
They sound like people who don't know what is basic or advanced as to electronics design.

The transformer won't work at 125kHz

dB / dt = V / ( N. Ae ), dB = -Bpk to +Bpk, dt = half cycle, [ Ae = 100mm^2, N = 2, ]

therefore, at 200kHz, with +/- 0.1T allows 16V driving on the 2T side

above 100mT @ 200kHz the cores will really cook, in fact they will cook above 100kHz, 100mT

( edit: it won't work at 250kHz either )

above 100mT @ 200kHz the cores will really cook,

Click to expand...

Thanks, its a Planar with a flat top and bottom.....its in a very thick aluminium enclosure.....so will have to look into ways of heatsinking it...possibly gap-padding it, to the chassis.
The LTC3723-1 has a 220pF CT capacitor, which means the oscillator is at 307kHz, which means a switching frequency of 153.5kHz.

At this 153.5kHz, i calculatate dB = +/-0.093T

actually it's 150mT each way, i.e. Bpk = 150mT

dB = V. dt / ( N. Ae ) = 18V . 3.33uS / ( 2 . 100E-6 ) = 0.2997 pk - pk

=> Bpk = 0.15

This could work for well heatsunk cores ....

3.5W core say @ 153kHz, 150mT pk,