mostafa272
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Hi
I make a tpr file that is for description of a one-bit full adder. I add it to L-edit with standard library(from SPR->place and route).the L-edit creates layouts for core and chip,but these layouts have some DRC errors that are about select to select spacing!
Also when I try to make a spice netlist, there is an other error about "n well wire"!
How can I solve these problems without manual changing on layouts?
I make a tpr file that is for description of a one-bit full adder. I add it to L-edit with standard library(from SPR->place and route).the L-edit creates layouts for core and chip,but these layouts have some DRC errors that are about select to select spacing!
Also when I try to make a spice netlist, there is an other error about "n well wire"!
How can I solve these problems without manual changing on layouts?