pisoiu, COME 2 C my problem.

[llrry]

It happened that recently I was bothered by a data acquisition problem.
I have a system base on one DSP.
and one FPGA implement 4 PWM channel and an ADC controller.
To test the ADC controller, I use 1 PWM channel to generate sinwave
and force the output to ADC input , and output the readed data to another PWM channel to observe.
Data exchange is controlled by DSP through FPGA.
My problem is very strange.
sometime there is no problem, but sometime the output contains many error.
Error is not like a sampling noise, compare the PWM source and target output:
follow well-->stop follow and hold /or jump and hold for a pretty long period-->and follow again.
But if I simply change the DSP operation clock, I never see the problem
happens.(I'm not sure it dissappears but the probability is much lower).

HOW do you think about my problem?

 

[pisoiu]

Well, you problem is indeed strange. One theory that I like says: If a high performance system generate the same results (right or wrong, no matter) running with with the same input variables, regardless of how often you process those variables, it means that the software inside it must be somehow ok. If the results are good or bad, that's programmer's fault. But if the system behave strange and generate chaotic results at consecutive processes, than check your PCB. The procedure described by you seem ok, but lemme ask you som' :
Such a system like yours definetely is a mixed analog-digital design. Two causes may exist.
1. check some details of your pcb: separate analog and digital power planes, do not route analog signals over digital planes and vice-versa, decouple well every digital IC with capacitors with self-resonant frequency much higher than knee frequency, route gnd and vcc pins of ic directly to power planes, not through long and thin traces, do not use vias on sensitive signals like sampling clock.
2. check routing inside FPGA. if your problem dissapears when lowering frequency, then you may have a tight condition inside FPGA algorythm, somewhere you may miss a setup/hold time for an input signal.

Also, from your description, I understood that you insert a sin signal obtained from a PWM. For this I think you use a converter from PWM to analog. How is this circuit powered? From digital power or from analog? I hope you did not connect digital ground and analog ground respectively digital vcc and analog vcc in more than one point.
Well, I hope this helps...lemme know.

 

[llrry]

hi,pisoiu:
Thank you very much for your guide.
First of all, I am not considering a layout problem. But probably you are
right, it comes from the improper deal with the digital/analog power and ground.
The PCB artworker is not an experienced one.
But I hope it's not that bad, since I have to layout once more before I solve this problem. And even now I can not locate the problem point exactly to the PCB.
My ADC is external AD7072, and working at a 8Mhz clock and 90Khz sampling frequncy.
And PWM carrier frequncy is 180Khz, VS a generated sinwave @350hz.
I use an OP-AMP to convert the PWM ourput to analog.

The FPGA operation clock is 16Mhz as well as my DSP. And regardless of a higher or lower clock, the problem do exsist as long as I clock the FPGA and DSP at a same frequency(but different source--I mean oscillator).

The amazing thing is if I change the DSP working clock to 10M or 25M.
but remain the FPGA working at 16M, I never see the problem.

I think the only check point is DSP read instruction. The read point changes when the main clock changes.

And I don't understand very much that is: the wrong states can last for
1MS or more, that means consecutive 80 samples are wrong.
I am afraid that the ADC goes to sleep mode due to some unknow reason. But even it went to sleep, it should be waked up immediately for the next sampling period.

These days, I am bothered with another project. So I can not focus on the problem for days. But I will be back to solve it soon.

As a matter of fact, I don't have much experience on high speed signal processing. And I don't realize how much it could be bad for my design. But anyway I will keep your advise in my mind.

It's hard to show you exactly my situation through these posts. But I'd like to show you the experience once I solve my problem.

Very much thanks again and have a nice day.