Pipelining to make the circuit work faster

[nishanthp68]

/The circuit synthesizes for 2 Mhz clock need to make it synthesize able for 200 MHz clock


// This module calculates the positive circle coordinate Y given X
// with a radius of R
// It is not very well written, but this provides students with
// an opportunity to improve the design
//
// Equation is that of a circle X^2 + Y^2 = R^2
// module calculates Y=sqrt(R^2-X^2)
// It performs no rounding...
// X and Y are both positive. (Only works in quadrant 1)
/

`timescale 1ns/10ps


module circ(clk, reset, pushin, Xin, Rin, pushout, Yout);
input clk,reset,pushin;
input [23:0] Xin,Rin;
output pushout;
output [23:0] Yout;

reg [23:0] Xl,Rl;
reg V1;

reg [47:0] X2,R2,diff,Diff;
reg V2;
reg V3;//previous push signal
//reg [15:0]V3;
reg [24:0] res;
reg [24:0] rv;


always @(negedge(clk) or posedge(reset)) begin
if(reset) begin
V1<=0;
Xl<=0;
Rl<=0;
end else begin
V1<= #1 pushin;
Xl<= #1 Xin;
Rl<= #1 Rin;
end
end

always @(negedge(clk) or posedge(reset)) begin
if(reset) begin
V2 <= 0;
X2 <= 0;
R2 <= 0;

end else begin
V2 <= #1 V1;
X2 <= #1 Xl*Xl;
R2 <= #1 Rl*Rl;
end

end

always @(negedge(clk) or posedge(reset)) begin
if(reset) begin
V3 <= 0;
diff <= 0;
end else begin
V3 <= #1 V2;
Diff <= #1 R2-X2;
end

end

integer ix;
always @(*) begin
res=0;
rv=0;
diff=Diff;
for(ix=0; ix < 24; ix=ix+1) begin
rv = { rv[22:0], diff[47:46] };
diff={ diff[45:0],2'b0};
if( { res[22:0],2'b1 } <= rv ) begin
rv=rv - { res[22:0],2'b1 };
res = { res[23:0],1'b1 };
end else res= { res[23:0],1'b0 };
end
end

assign pushout=V3;
assign Yout = res[23:0];

endmodule



LAST PART OF THE PROGRAM EDITED

integer ix;
always @(*) begin
res=0;
rv=0;
diff=Diff;
for(iy=0;iy<16;iy=iy+1)
// if pushout of previous block is one continues
for(ix=0; ix < 2; ix=ix+1) begin
rv = { rv[22:0], diff[47:46] };
diff={ diff[45:0],2'b0};
if( { res[22:0],2'b1 } <= rv ) begin
rv=rv - { res[22:0],2'b1 };
res = { res[23:0],1'b1 };
end else res= { res[23:0],1'b0 };
end
end
assign pushout[iy]=V3;
end
assign Yout = res[23:0];

Similarly I did it for 24 divisions , but still its not synthesizing for 200 MHz. How can I do that without using a two flag model

 

[FvM]

The critical point is surely the looped calculation which produces a huge chain of substractors. You could e.g. think of completely pipelining it, placing a register level for each iteration.

 

[nishanthp68]

That was very helpful , but still I cannot get my timing considerations, can i place two pushout signals within one iteration?

 

[FvM]

but still I cannot get my timing considerations, can i place two pushout signals within one iteration?

May be a problem of the 200 MHz clock frequency. You mean pipelining the individual substractors itself? That's not easy in behavioral code. You can try to place double registers behind the substractor and enable register retiming in your synthesis tool. It may be able to "pull" a register inside the substractor logic. Using vendor libraries in structural code is usually a more flexible way to synthesize clocked arithmetic and control pipelining.

You also should analyze thoroughly where's the actual bottleneck of your design by going through the timing analysis details.

 

[nisshith]

i think you should also pay attention to the point where you are multiplying to 24 bits numbers and generating a 48 bit output. Multiplying two 24 bits number requires very large hardware. Pipe-lining that multiplication could help.

 

[FvM]

i think you should also pay attention to the point where you are multiplying to 24 bits numbers and generating a 48 bit output. Multiplying two 24 bits number requires very large hardware. Pipe-lining that multiplication could help.

Right, I didn't notice the multiply. If it's critical also depend on the availablity of hardware multipliers in your FPGA family, which hasn't been mentioned yet. The comment refers once more to the importance of timing analysis.

 

[nishanthp68]

Thank you guys for your help , I am still very new to programming

I had not run the program before , I just had done it theoretically


integer ix;
always @(*) begin
res=0;
rv=0;
diff=Diff;
for(ix=0; ix < 24; ix=ix+1) begin
rv = { rv[22:0], diff[47:46] };
diff={ diff[45:0],2'b0};
if( { res[22:0],2'b1 } <= rv ) begin
rv=rv - { res[22:0],2'b1 };
res = { res[23:0],1'b1 };
end else res= { res[23:0],1'b0 };
end
assign pushout[ix]=V3;
end
assign Yout = res[23:0];

it says that I cant use continuous assignment for my pushsignal Can you please help me with this. what other options I have to make these changes .

Also can you please suggest me from where I can learn programming ??

Thanking You in advance