pipelined adc problem,ergent！

[lhlbluesky]

i have designed a pipelined adc of 10bit 1.5bit per stage,when i connect the nine stages together,i find that the output of the third MDAC begins to degrade(for a signal vdc input signal),and more severely with the increase of the number of stages,for the last stage,the output is very very worse;besides,the output of the sixth sub-adc is wrong for the first clock cycle,and so the seventh to ninth stages which are also wrong for the first clock cycle,i don't know why.
is it the reason of the GBW,but i change the GBW by 10%,it improves little;
any other reasons?
can anyone give me some advice,pls?
thanks for all reply.

 

[naalald]

Hi,
Make sure your opamp in each stage settles in the time the next stage is supposed to sample. In addition to the opamp's GBW, it's gain and parasitic capacitances are important, too. The timing of the clocks is also important. You can compensate the opamp's GBW with the timing a little. And at last make sure you perform bottom-plate sampling correctly.

 

[lhlbluesky]

i know that,besides,how to realize RSD for pipelined adc?how to realize the delay cell and what's the timing of RSD?

 

[naalald]

Hi lhlbluesky,
For delay elements you can use transistor-level flip-flops.
For realizing the residue stage and their timings see thesis like Abo. Here is the link:

Hope it helps you!

 

[dendrite]

Use Verilog-A simulation to determine the causal link between the stages2 and stage3.

 

[mohsen2010]

Hi all

I have problem with my MDAC.
I have designed a fully differential opamp with UGB=680MHz, DC gain=67db, PM=61 deg, input common-mode voltage = 0.75v but the output common mode voltage =0.5v .This opamp is designed for a pipelined ADC and is used in the MDAC. The signal CM is also 0.5 volt

The problem is that this opamp doesn't work! I tried to test it in a simple Charge-Redistribution SHA circuit with sampling rate of 4 MHz, but both of the outputs are always saturated in the hold phase and consequently the differential output is zero.

I know that in theory, the opamp of a CR SHA doesn't need to have equal input and output CM voltage. So what is the problem?

How did you implement your mdac in transistor level? Is your opamp fully differential ? Are the input and output common-mode voltages of opamp different?