Well, in my opinion, your professor seems to be right. The additional register (shown in red) in the second figure will ensure that there are same number of cycles from Register to data memory. If that register is omitted. then there would be a mismatch in pipeline stages.
But yes, it is also important to note that how does this architecture work. For example, if the working ensures that the register data is latched until the respective address of memory becomes available, then the first figure would work fine either. But if the design is fully pipelined, then you can see that data from registers will become available one cycle earlier than its respective address (Structural Hazard).
I hope that it makes the point clear.
Thanks.
MSBR