Pipeline ADC:Problems about different results with different simulation times?

Status
Not open for further replies.
G

guanglei

Newbie level 4
Joined
Aug 16, 2010
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,312
I am simulating 8 bit pipeline ADC with verilog A model, sampling frequency is 16k.When I ran the transient simulation with a input ramp, the first time I choose simulation time 1/16k*512=32ms, the output is correct; the second time I doubled the simulation time and keep everything the same but result is wrong. I don't know why the result changed because of the different simulation time,anyone can give me some idea,thanks!




Guanglei
 


I am attaching the second result of the following ideal 8 bit DAC，thanks!
 

Are you referring to the spikes on the waveform as being wrong? Those may be real and they were just too fast to show up in the first simulation.
 

I am attaching the two simulation results:32ms and 64ms.you can see for the 32ms simulation, the pulse step increases monotonically; but for 64ms simulation, the output is even not steps,thanks!
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…