Pipeline ADC DNL and INL simulation Question

[4s]

pipeline　dnl

I using a slow Ramping signal(ideal) to simulate the DNL of a 10bit pipeline ADC.
I found that there is non-monotonicity digital output code. In this cases, how can I plot the DNL curves and INL?

 

[_pv]

dnl in pipeline

Diff nonlinearity is the difference beetwen widths of ideal ADC quant and real.
nonmonolicity appears when DNL > 1LSB i.e. one of real acd quants became wider then 2 ideal quants and thus "eat" the neibghour quant.

in the situation with ideal ADC but when one quant is just missing in the point you have missing code, value of DNL there is should be 1LSB (ideal = 1lsb, real = 2lsb), in the next point it should be ~ -1LSB. beacuse "eaten" quant width is 0 instead of 1 LSB. (ideal = 1lsb, real 0 lsb).

to get INL you should take differencr between voltage applied to ADC input and result of ADC measurement (code / 1024 * Vref)
or you could just integrate DNL.

 

[mohsen asloni]

You said u saw a non-monotonocity in transfer function of ADC. would u like to describe your opinion about it? I have your problem Dear 4S