pipe lining in dataflow in verlog

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i understood that but i have to do it in verilog and in pipelining i have to call modules, which is not applicable in behavioral modelling means under always(process in VHDL), so do you have any suggestion abt that.....????
 

Hi

Of course you cannot call modules in the always block in verilog, but if you plan to do pipelining using modules, then you can use ENABLE signal for your modules, so at certain conditions you can enable or disable the modules inside the always block.

Hope this helps
 

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