Pipe line insertion between fifos

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d4red

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Does anyone have pipe line design example to insert one clock stage between two fifos? If you can share a script, that would be great help.
 

d4red said:
Does anyone have pipe line design example to insert one clock stage between two fifos?
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Presuming you are solely asking for Pipeline and already have an implementation for the FIFO´s, this task could not be achieved by just adding an useless FIFO ( sized for 1 Flip Flop ) between these other FIFO´s ?



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    d4red

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Hmm... that's smart solution. I just need to do a little tune up on the one depth fifo, since the data needs some operations. Thanks.
 

As andre told, just add FFs sampling stage (won't necessarily have to be as another FIFO).
You can instate those FFs manually in the verilog code.
 

Only flop is not enough. I have to implement valid/stall, since I want to crash bubble.
 

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