Pins that function as both inputs and outputs

Dear all,
could anyone please teach me how to create pins that can be use as input pin as well as output pin (in VHDL)? I've tried using:
twowayPin : INOUT std_logic_vector(63 DOWNTO 0);

but whenever i compile i got the follwing warning:
Warning: TRI or OPNDRN buffers permanently enabled

and the default signal has become all ZZZZZZZZZZZ
if i try to simulate a data input, it will give a warning that signal contention happens..

pls help pls help... thank you very much

Hello aeneas81,

take a look at the following code:

ENTITY bidirektional IS
PORT( en_ab, en_ba: IN std_ulogic;
dbus_a: INOUT std_logic_vector(7 DOWNTO 0);
dbus_b: INOUT std_logic_vector(7 DOWNTO 0) );
END bidirektional;
ARCHITECTURE behave OF bidirektional IS
BEGIN
bidir_module: PROCESS(en_ab, en_ba, dbus_a, dbus_b)
BEGIN
-- write from port a to port b
IF ( en_ab = '1' AND en_ba = '0' ) THEN
dbus_b <= dbus_a;
dbus_a <= (OTHERS => 'Z');
-- write from port b to port a
ELSIF ( en_ab = '0' AND en_ba = '1' ) THEN
dbus_a <= dbus_b;
dbus_b <= (OTHERS => 'Z');
-- Tristate port a and b
ELSIF ( en_ab = '0' AND en_ba = '0' ) THEN
dbus_a <= (OTHERS => 'Z');
dbus_b <= (OTHERS => 'Z');
-- Both ports are enabled
ELSE
dbus_a <= dbus_b;
dbus_b <= dbus_a;
ASSERT FALSE REPORT
"Both Tristate Buffer are enabled!" SEVERITY NOTE;
END IF;
END PROCESS bidir_module;
END behave;


Bye,
cube007

thanks dude, i'll try on the code. by the way, what's a std_ulogic type?

I've found the answer myself. Thanks a lot!


The std_ulogic type
This type is used to represent the value of a digital signal in a wire. For general use, you probably want the std_logic instead. A signal or variable of this type can take on the following values:

'U': uninitialized. This signal hasn't been set yet.
'X': unknown. Impossible to determine this value/result.
'0': logic 0
'1': logic 1
'Z': High Impedance
'W': Weak signal, can't tell if it should be 0 or 1.
'L': Weak signal that should probably go to 0
'H': Weak signal that should probably go to 1
'-': Don't care.
The basic VHDL logic operations are defined on this type: and, nand, or, nor, xor, xnor, not. They can be used like the built-in operations on the bits.

cube, u really made my day!!! thank you so much!! finally i managed to solve a large problem with my design. Thanks! n god bless

aeneas81 said:

cube, u really made my day!!! thank you so much!! finally i managed to solve a large problem with my design. Thanks! n god bless

Click to expand...

Hello aeneas81,

You’re welcome. I advise you to get some VHDL books/ebooks for consulting. You can find some of these in the ebook Section.

Bye and happy coding,
cube007