Pin type options in Cadence Virtuoso

[Junus2012]

Hello,

I have a question about the options for creating pins in Cadence virtuoso, there are many types to select, for example, power, ground, signal, clock ..etc.

Do they have physical meaning during the circuit simulation or real chip fabrication after exporting the gds file?

I have realized lately that I am using "signal" type even for creating the vdd! and the gnd! global and the clock pins in my design.



Thank you

Regar

 

[dick_freebird]

I only use the basic library ipin (schipin), opin, iopin. These
come with some SRC rules associated (open input, shorted output,
etc.) and I imagine there may be other schematic constraints
applied to these others.

I generally make everything "iopin" to avoid most of that meddling.
But I do 90% analog, and the digital, "analog style"....

 

[timof]

I wish there would be "?" button next to each entry / term / concept that would provide an immediate quick help to the user (especially - to a novice or infrequent user), in all EDA (and non-EDA) software tools - about its meaning, purpose, significance, implications, options, etc.

In a post-layout netlist (DSPF, SPEF, etc.), each port and instance pin has a description (single letter) explaining its purpose - I (input), O (output), B (bi-directional), maybe more.
Like many other things in a DSPF file, these entries have mono effect on electrical simulation.
They are used as annotations, to pass the design intent to downstream tools - so that their behavior, handling of the nets, pins, etc. is affected by the design intent.

Passing the design intent through the design flow is a very good thing, but in many occasions - it is not done, which is very bad.
People and tools have to spend extra efforts to "understand" what was the intent and needs to be done, and very often do much more than needed.

 

[smlogan_eda]

have a question about the options for creating pins in Cadence virtuoso, there are many types to select, for example, power, ground, signal, clock ..etc.

Do they have physical meaning during the circuit simulation or real chip fabrication after exporting the gds file?

I have realized lately that I am using "signal" type even for creating the vdd! and the gnd! global and the clock pins in my design.

Dear Junus2012,

If you happen to have the "Senan" handle on the Cadence Forums, I believe you asked this same question on the Cadence Forums. This is the question from the Cadence Forums:

"I have a question about the options for creating pins in Cadence virtuoso, there are many types to select, for example, power, ground, signal, clock ..etc.

Do they have physical meaning during the circuit simulation or real chip fabrication after exporting the gds file?

I have realized lately that I am using "signal" type even for creating the vdd! and the gnd! global and the clock pins in my design."

Andrew and I responded at URL:

Pin type options in Cadence Virtuoso - Custom IC Design - Cadence Technology Forums - Cadence Community

Hello, I have a question about the options for creating pins in Cadence virtuoso, there are many types to select, for example, power, ground, signal, clock ..etc

community.cadence.com

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Shawn