m.m.m
Newbie level 4
Hi everyone,
I’ve run into an issue with my design when using Quantus QRC (Assura) for parasitic extraction and simulating the design in Cadence Virtuoso with Maestro.
After running Quantus QRC on my layout, it generated a SPICE netlist for the extracted view. However, I’ve noticed that the pin order in the subcircuit within this SPICE netlist is different from the pin order used when Maestro instantiates the same subcircuit during simulation. As a result, my design doesn’t function properly in the simulation.
Here's the instance in the schematic view:
and the created netlist for simulation:
But the extracted hspice subckt has the following port config:
And the layout pins have the same names and labels as the ones in schematic, and LVS gives no errors.
I can manually reorder the subckt pin order in the netlist but it would be rewritten each time I extract the netlist, which is not ideal at all.
So I'd appreciate your suggestions.
I’ve run into an issue with my design when using Quantus QRC (Assura) for parasitic extraction and simulating the design in Cadence Virtuoso with Maestro.
After running Quantus QRC on my layout, it generated a SPICE netlist for the extracted view. However, I’ve noticed that the pin order in the subcircuit within this SPICE netlist is different from the pin order used when Maestro instantiates the same subcircuit during simulation. As a result, my design doesn’t function properly in the simulation.
Here's the instance in the schematic view:
and the created netlist for simulation:
But the extracted hspice subckt has the following port config:
And the layout pins have the same names and labels as the ones in schematic, and LVS gives no errors.
I can manually reorder the subckt pin order in the netlist but it would be rewritten each time I extract the netlist, which is not ideal at all.
So I'd appreciate your suggestions.