PIC24F04KA200 and deep sleep mode

[sztibi82]

Hi All, I try to put the PIC24F04KA200 into deep sleep for about 1 minute and then wake it up.
For now I didn't manage to make the controller to go into deep sleep at all.

The flags are set as follow:

// FGS
#pragma config GWRP = OFF // General Segment Code Flash Write Protection bit (General segment may be written)
#pragma config GCP = OFF // General Segment Code Flash Code Protection bit (No protection)

// FOSCSEL
#pragma config FNOSC = FRCDIV // Oscillator Select (8 MHz FRC oscillator with divide-by-N (FRCDIV))
#pragma config IESO = ON // Internal External Switch Over bit (Internal External Switchover mode enabled (Two-Speed Start-up enabled))

// FOSC
#pragma config POSCMOD = NONE // Primary Oscillator Configuration bits (Primary oscillator disabled)
#pragma config OSCIOFNC = OFF // CLKO Enable Configuration bit (CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0>))
#pragma config POSCFREQ = HS // Primary Oscillator Frequency Range Configuration bits (Primary oscillator/external clock input frequency greater than 8 MHz)
#pragma config SOSCSEL = SOSCHP // SOSC Power Selection Configuration bits (Secondary oscillator configured for high-power operation)
#pragma config FCKSM = CSDCMD // Clock Switching and Monitor Selection (Clock switching is disabled, Fail-Safe Clock Monitor is disabled)

// FWDT
#pragma config WDTPS = PS32768 // Watchdog Timer Postscale Select bits (1:32,768)
#pragma config FWPSA = PR128 // WDT Prescaler (WDT prescaler ratio of 1:128)
#pragma config WINDIS = OFF // Windowed Watchdog Timer Disable bit (Standard WDT selected; windowed WDT disabled)
#pragma config FWDTEN = ON // Watchdog Timer Enable bit (WDT enabled)

// FPOR
#pragma config BOREN = BOR3 // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware; SBOREN bit disabled)
#pragma config PWRTEN = ON // Power-up Timer Enable bit (PWRT enabled)
//#pragma config BORV = 18V // Brown-out Reset Voltage bits (Brown-out Reset set to lowest voltage (1.8V))
#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RA5 input pin disabled)

// FICD
#pragma config ICS = PGx2 // Reserved (PGC2/PGD2 are used for programming the device)

// FDS
#pragma config DSWDTPS = DSWDTPSF // Deep Sleep Watchdog Timer Postscale Select bits (1:2,147,483,648 (25.7 Days))
#pragma config DSLPBOR = ON // Deep Sleep Zero-Power BOR Enable bit (Deep Sleep BOR enabled in Deep Sleep)
#pragma config DSWDTEN = ON // Deep Sleep Watchdog Timer Enable bit (DSWDT enabled)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

#define FCY 4000000
#define TRUE 1
#define FALSE 0

#include "xc.h"
#include <p24F04KA200.h>
#include <libpic30.h>

the routine for starting the deep sleep are:

void DeepSleepConfiguration(void)
{
DSCONbits.DSEN = 1;
asm("nop");
asm("nop");
asm("nop");
asm("pwrsav #0");
}

Alternatively I tried this

void DeepSleepConfiguration(void)
{
    asm("bset DSCON, #15");
asm("nop");
asm("nop");
asm("nop");
asm("pwrsav #0");
}

please can advice what to do to get into deep sleep.

 

[FvM]

How do you determine that DS isn't entered?
You know that DS won't be executed in debug mode?

 

[sztibi82]

How do you determine that DS isn't entered?
You know that DS won't be executed in debug mode?

The microcontroller is programmed, and checked on board. The current is not dropping when it should enter into deep sleep.

 

[Aussie Susan]

Not your problem but don't include the processor specific file - the <xc.h> does all of that for you.
There is an entry in the silicon errata about deep sleep but it is more about the wake-up sources and probably not related to your problem.
As you are using the XC16 compiler, it might be easier to use the '__builtin_pwrsav' macro than your own assembler instructions.
Are you sure that none of the 'wake up'conditions are not being met? Looking at the FRM section 39.3.1, it says that coincident interrupts are held off until the chip is in sleep mode and then used to wake up the device. (I also see the "Note at the top of page 93 of the data sheet that says pending interrupts are cleared on entry to deep sleep - I reconcile these by the use of the words 'pending' and 'coincident'.)
I would suggest that you (say) set an I/O pin just before starting the deep sleep sequence and clear it just after the wake-up (in the POR sequence). That way you can use a scope to see the length of time actually taken - you can then tell the difference between the deep sleep being ignored and the sleep being entered and exited - the wake-up times being given in the FRM table 39-1.)
Have you tried to turn off both the WDT and the DSPWDT?
Have you checked the RCON and DSCON registers to determine the actual source of the wake-up (if any)?
Susan