ragav4456
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Hi frnds
I have doubt in USART1 Receive PIC18f45k22 controller. I am using C18 compiler. Could you please explain the interrupt vector and isr function.?
I have doubt in USART1 Receive PIC18f45k22 controller. I am using C18 compiler. Could you please explain the interrupt vector and isr function.?
Code:
#include <p18f45k22.h>
#include <usart.h>
#include <adc.h>
#include <delays.h>
#include <stdlib.h>
#include <string.h>
#define EAUSART_V11
// CONFIG1H
#pragma config FOSC = HSMP // Oscillator Selection bits (HS oscillator (medium power 4-16 MHz))
#pragma config PLLCFG = OFF // 4X PLL Enable (Oscillator used directly)
#pragma config PRICLKEN = OFF // Primary clock enable bit (Primary clock can be disabled by software)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
// CONFIG2L
#pragma config PWRTEN = OFF // Power-up Timer Enable bit (Power up timer disabled)
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 190 // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)
// CONFIG2H
#pragma config WDTEN = OFF // Watchdog Timer Enable bits (Watch dog timer is always disabled. SWDTEN has no effect.)
#pragma config WDTPS = 1 // Watchdog Timer Postscale Select bits (1:1)
// CONFIG3H
#pragma config CCP2MX = PORTB3 // CCP2 MUX bit (CCP2 input/output is multiplexed with RB3)
#pragma config PBADEN = OFF // PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
#pragma config CCP3MX = PORTE0 // P3A/CCP3 Mux bit (P3A/CCP3 input/output is mulitplexed with RE0)
#pragma config HFOFST = OFF // HFINTOSC Fast Start-up (HFINTOSC output and ready status are delayed by the oscillator stable status)
#pragma config T3CMX = PORTC0 // Timer3 Clock input mux bit (T3CKI is on RC0)
#pragma config P2BMX = PORTD2 // ECCP2 B output mux bit (P2B is on RD2)
#pragma config MCLRE = EXTMCLR // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)
// CONFIG4L
#pragma config STVREN = OFF // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
#pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
// CONFIG5L
#pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
#pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
#pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
#pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)
// CONFIG5H
#pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
// CONFIG6L
#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)
// CONFIG6H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
// CONFIG7H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
//#pragma interrupt resv_isr
unsigned int uiIcnt;
unsigned char Recv_Data='s';
void resv_isr()
{
if(PIR1bits.RC1IF == 1)
{
Recv_Data = Read1USART();
PIR1bits.RC1IF = 0;
LATEbits.LATE0 = ~LATEbits.LATE0;
}
LATEbits.LATE0 = ~LATEbits.LATE0;
}
void main()
{
TRISAbits.TRISA0=0;
TRISCbits.TRISC4=0;
TRISCbits.TRISC6=0;
TRISCbits.TRISC7=1;
TRISEbits.TRISE1=0;
PORTCbits.RC4=0;
PORTEbits.RE1=0;
PORTCbits.RC7=0;
CloseADC();
PMD1=0xff; //Peripheral Module disable Register
PMD2=0x0f;
WDTCONbits.SWDTEN = 0;
ADCON0bits.ADON = 0;
OSCCON = 0x00;
OSCCON2 = 0x00;
OSCTUNE = 0x00;
/* Enable UART1*/
Open1USART(USART_TX_INT_OFF & USART_RX_INT_ON & USART_ASYNCH_MODE & USART_EIGHT_BIT & USART_CONT_RX & USART_BRGH_HIGH , 77);
/* Enable UART2*/
Open2USART(USART_TX_INT_OFF & USART_RX_INT_ON & USART_ASYNCH_MODE & USART_EIGHT_BIT & USART_CONT_RX & USART_BRGH_HIGH , 77);
Delay100TCYx(100);
baud1USART(BAUD_IDLE_CLK_LOW & BAUD_8_BIT_RATE & BAUD_WAKEUP_OFF & BAUD_AUTO_OFF);
baud2USART(BAUD_IDLE_CLK_LOW & BAUD_8_BIT_RATE & BAUD_WAKEUP_OFF & BAUD_AUTO_OFF);
RCSTA1bits.CREN = 1; // Enable Receiver
RCSTA1bits.SPEN = 1; // Serial Port enable
RCSTAbits.ADDEN = 0; // Disable address detection
RCSTAbits.RX9 = 0; // 8 bit data Reception
BAUDCON1bits.DTRXP = 0; // Receiver data not invertered
BAUDCON1bits.RCIDL = 1; // Receiver is Idle
BAUDCON1bits.WUE = 0; // Receiver operating normally
BAUDCON1bits.BRG16 = 0; // 8 bit Baud rate enable
BAUDCON1bits.ABDEN = 0; // Auto baud detect disabled
INTCONbits.GIE = 1; // Enable Global Interrupt
INTCONbits.PEIE = 1; // Enable Periperal Interrupt
RCONbits.IPEN = 1; // Enable Interrupt Priority
IPR1bits.RC1IP = 1; // Receive UART1 high Interrupt priority
IPR3bits.RC2IP = 1; // Receive UART2 high Interrupt priority
PIE1bits.RC1IE = 1; // Receive UART1 Interrupt enable
PIE3bits.RC2IE = 1; // Receive UART2 Interrupt enable
PMD0bits.UART1MD = 0; // UART1 Module enabled
PMD0bits.UART2MD = 0; // UART2 Module enabled
Delay100TCYx(100);
while(1)
{
LATEbits.LATE1 = 1;
Delay10KTCYx(200);
while (!DataRdy1USART());
if(DataRdy1USART())
{
Recv_Data = Read1USART();
PIR1bits.RC1IF = 0;
}
putc2USART('s');
Delay10KTCYx(200);
Write1USART(Recv_Data);
LATEbits.LATE1 = 0;
Delay10KTCYx(200);
}
}