[SOLVED] pic18f4520 input output problem

[abc_de]

hi
i am trying to use pic18f4520 in basic input and output purpose unfortunately i am getting some unexpected response.


code flow is if switch pressed then PORTA is zero else PORTA is high.
result > if i press switch then PORTA is 3.8v else 5v
i do not know why PORTA is not getting 0v

#include <xc.h>

// PIC18F4520 Configuration Bit Settings

// 'C' source line config statements

// CONFIG1H
#pragma config OSC = INTIO67    // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRT = OFF        // Power-up Timer Enable bit (PWRT enabled)
#pragma config BOREN = OFF      // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
#pragma config BORV = 3         // Brown Out Reset Voltage bits (Minimum setting)

// CONFIG2H
#pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = PORTC   // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
#pragma config LPT1OSC = OFF    // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = OFF     // Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
#pragma config LVP = OFF        // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-001FFFh) not code-protected)
#pragma config CP1 = OFF        // Code Protection bit (Block 1 (002000-003FFFh) not code-protected)
#pragma config CP2 = OFF        // Code Protection bit (Block 2 (004000-005FFFh) not code-protected)
#pragma config CP3 = OFF        // Code Protection bit (Block 3 (006000-007FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) not write-protected)
#pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) not write-protected)
#pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

#include <xc.h>

void intialisation(void);


void intialisation(void)
{
    OSCCON=0X74; 
    /*PORT A*/
    TRISA=0x00;
    PORTA=0x00;
    LATA=0x00;
  
    ADCON1=0x0f;
    CMCON=0x07;// comparator off 
    CVRCON=0x00;
    
    /*PORT B*/
    PORTB=0x00; 
    TRISB=0x3f; 
    INTCON=0x00;
    INTCON2=0x80;// all port b pull ups are disable  



}
void main(void)
{
    intialisation();
    
    while(1)
    {
        if(PORTBbits.RB0==0) LATA=0X00;
        else  LATA=0Xff;
       
        if(PORTBbits.RB1==0) LATA=0X00;
        else  LATA=0Xff;
        
        if(PORTBbits.RB2==0) LATA=0X00;
        else  LATA=0Xff;
         
        if(PORTBbits.RB3==0) LATA=0X00;
        else  LATA=0Xff;
        
        if(PORTBbits.RB4==0) LATA=0X00;
        else  LATA=0Xff;
     
        if(PORTBbits.RB5==0) LATA=0X00;
        else  LATA=0Xff;
                  
                      
       
    }
    return;
}

:drevil::drevil:

 

[betwixt]

How is the switch connected?

I am guessing you have the switch connected to one of the pins on PORTB. If that is the case you have two problems:

1. You have the PORTB pull-ups disabled so any pin not connected (including through open switches) to VSS or VDD is floating and can adopt any logic state at any time.

2. If you are not driving all the PORTB inputs simultaneously and to the same logic level, the output from LATA will be switching from high to low repeatedly in the while() loop. As the voltage would be rising and falling, a voltmeter will read the average voltage which would be somewhere between 0V and 5V.

Brian.

 

[Aussie Susan]

What exactly is the logic you are intending to implement?
The way I read your description was that is *any* PORTB pin (or perhaps any of pins RB0 to RB5) was high then set all of the PORTA bits high - in other words you are treating PORTB as an 'OR' gate.
If that is the case then your implementation is wrong and should be something like:

    if(PORTB & 0x3f) LATA = 0;
    else LATA = 0xff;

Susan

 

[abc_de]

great information.
problem was associated with software part. now its solved.:lol: