PIC18 interrupt on two-word instructions question

pic18 interrupt

Hello friends,

I am really having trouble with the MikroC pointer implementation.

Below is a sample code snippet using a pointer of my code.

On a closer look the compiler uses POSTINC register instead of INDF. Using POSTINC will increment the FSR register when reaching the pointed object.


I have some questions:

1.) On mikroC compiler: Is there any work around so that the compiler will use the INDF register instead of POSTINC in reaching the pointed object?



My concern is when an interrupt occurs when the first word of this instruction is excuted

$C0C4 FFE6 MOVFF FARG_write_char+0, POSTINC1

The FSR registers have been set before this instruction but when the first instruction is decoded, the FSR is incremented because of using POSTINC register.

Any idea how to resolve this issue?


Thanks,
Neo


;void write_char(char character){*gRAM_LOC = character; gRAM_LOC++;}
$C041 FFE1 MOVFF _gRAM_LOC, FSR1L
$C042 FFE2 MOVFF _gRAM_LOC+1, FSR1H
$C0C4 FFE6 MOVFF FARG_write_char+0, POSTINC1
$4A41 INFSNZ _gRAM_LOC, 1, 0
$2A42 INCF _gRAM_LOC+1, 1, 0
$0012 RETURN

postinc pic18

neoaspilet11 said:

I am really having trouble with the MikroC pointer implementation.

Click to expand...

IMHO, the translation will not be a problem even at any cycle of MOVFF.
PIC18 has same interrupt latency (3~4 Tcy) whether 1 or 2 cycle instruction,
the FNOP (forced NOP) dummy cycle(s) will be executed to maintain consistent interrupt latency.
Due to the MOVFF updates the destination on 2nd cycle's Q4,
the only limitation is using MOVFF with any one of PCL,TOSU,TOSH,TOSL as destination. (PC will be stored on stack during Q3)

neoaspilet11 said:

$C0C4 FFE6 MOVFF FARG_write_char+0, POSTINC1

The FSR registers have been set before this instruction but when the first instruction is decoded, the FSR is incremented because of using POSTINC register.

Click to expand...

Since the MOVFF with POSTINC as destination, the FSR should be increased after the 2nd cycle's Q4.