No, you are confusing input leakage with the internal pull-up current source. I'll try to explain:
Input leakage is the current drawn by an input pin when you drive it to a logic high level. Think of it as the reading you would get if you connected a current meter between VDD and an input pin. Ideally it would be zero but there is always a small current 'the leakage' caused by impurities in the silicon that lets a little flow through.
The pull-up current is intentional and you can turn it on or off under program control. It is a facility added by the manufacturer so you can make a pin default to a high state if nothing is driving it. As a consequence, to make the pin go to a logic low state you have to overcome the 'pull-up', pulling the pin down by drawing current out of it through an external connection. Think of it as the current you would measure if you connected a current meter between the pin and VSS and had the pull-up turned on. Note that a pin with nothig driving it and it's pull-up disabled draws such small current that it will pick up static levels around it and it's logic level would be unpredictable.
Note that there is a huge difference between 25nA and 25uA (1,000 times) even though both are quite small.
Brian.