romel_emperado
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PIC18f4550 does not support MDD format i was told that it would be fixed in the next versions.. you can use SPI format for that purpose... its easy.. you just need to need to read and write FAT file system..........
MMC <--SPI-->PIC18f4550 <---USART--->PC
I want to read/write in the MMC using SPI protocol then the data to be written is from PC via UART.. is it possible??
the data trying to write is wav file.. is it possible?
A single transmission error can possibly corrupt the wave data. That's why people prefer special encoding and transmission protocols with consistency checks for binary data.
However, the said problem is far beyond this thread's topic. I generally think, people shouldn't encourage the original poster to continue the thread like an off-topic chat or personal blog. Strictly spoken, it's against the forum rules.
void shift_right()
{
char c;
if(P1 == 0x04)
{
P2 = 0xA0;
for(c=0; c<3; c++)
{
delay_ms(1000);
P2 = P2 >> 1;
}
}
hi have something to ask... hehe
I did a shift right routine as a laboratory exercise of one of my subjects but I think there's another way of writing better than this code...
}PHP:void shift_right() { char c; if(P1 == 0x04) { P2 = 0xA0; for(c=0; c<3; c++) { delay_ms(1000); P2 = P2 >> 1; } }
plz help me i m beginner in pic and MPLab.......in the pic 16f877a i use timer0.....and than i use T0CON (timer0 control). the MPLab complier give the :
Error [192] F:\PIC16F877A\MPLab\test_2.c; 10.1 undefined identifier "T0CON"
plz plz help me.!
5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
Additional information on the Timer0 module is
available in the PICmicro® Mid-Range MCU Family
Reference Manual (DS33023).
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If the TMR0 register is written, the increment
is inhibited for the following two instruction cycles.
The user can work around this by writing an adjusted
value to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit, T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the rising
edge. Restrictions on the external clock input are
discussed in detail in Section 5.2 “Using Timer0 with
an External Clock”.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The
prescaler is not readable or writable. Section 5.3
“Prescaler” details the operation of the prescaler.
5.1 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
bit TMR0IF (INTCON<2>). The interrupt can be
masked by clearing bit TMR0IE (INTCON<5>). Bit
TMR0IF must be cleared in software by the Timer0
module Interrupt Service Routine before re-enabling
this interrupt. The TMR0 interrupt cannot awaken the
processor from Sleep since the timer is shut-off during
Sleep.
C:\Program Files\HI-TECH Software\PICC\9.81\include
Code C - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 #ifndef _HTC_H_ #warning Header file pic16f877a.h included directly. Use #include <htc.h> instead. #endif /* header file for the MICROCHIP PIC microcontroller * 16F877A */ #ifndef __PIC16F877A_H #define __PIC16F877A_H // // Configuration mask definitions // // Config Register: CONFIG #define CONFIG 0x2007 // Oscillator Selection bits // RC oscillator #define FOSC_EXTRC 0xFFFF // HS oscillator #define FOSC_HS 0xFFFE // XT oscillator #define FOSC_XT 0xFFFD // LP oscillator #define FOSC_LP 0xFFFC // Watchdog Timer Enable bit // WDT enabled #define WDTE_ON 0xFFFF // WDT disabled #define WDTE_OFF 0xFFFB // Power-up Timer Enable bit // PWRT disabled #define PWRTE_OFF 0xFFFF // PWRT enabled #define PWRTE_ON 0xFFF7 // Brown-out Reset Enable bit // BOR enabled #define BOREN_ON 0xFFFF // BOR disabled #define BOREN_OFF 0xFFBF // Low-Voltage (Single-Supply) In-Circuit Serial Programming Enable bit // RB3/PGM pin has PGM function; low-voltage programming enabled #define LVP_ON 0xFFFF // RB3 is digital I/O, HV on MCLR must be used for programming #define LVP_OFF 0xFF7F // Data EEPROM Memory Code Protection bit // Data EEPROM code protection off #define CPD_OFF 0xFFFF // Data EEPROM code-protected #define CPD_ON 0xFEFF // Flash Program Memory Write Enable bits // Write protection off; all program memory may be written to by EECON control #define WRT_OFF 0xFFFF // 0000h to 00FFh write-protected; 0100h to 1FFFh may be written to by EECON control #define WRT_256 0xFDFF // 0000h to 07FFh write-protected; 0800h to 1FFFh may be written to by EECON control #define WRT_1FOURTH 0xFBFF // 0000h to 0FFFh write-protected; 1000h to 1FFFh may be written to by EECON control #define WRT_HALF 0xF9FF // In-Circuit Debugger Mode bit // In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins #define DEBUG_OFF 0xFFFF // In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger #define DEBUG_ON 0xF7FF // Flash Program Memory Code Protection bit // Code protection off #define CP_OFF 0xFFFF // All program memory code-protected #define CP_ON 0xDFFF // // Special function register definitions // // Register: INDF volatile unsigned char INDF @ 0x000; // bit and bitfield definitions // Register: TMR0 volatile unsigned char TMR0 @ 0x001; // bit and bitfield definitions // Register: PCL volatile unsigned char PCL @ 0x002; // bit and bitfield definitions // Register: STATUS volatile unsigned char STATUS @ 0x003; // bit and bitfield definitions volatile bit CARRY @ ((unsigned)&STATUS*8)+0; volatile bit DC @ ((unsigned)&STATUS*8)+1; volatile bit ZERO @ ((unsigned)&STATUS*8)+2; volatile bit nPD @ ((unsigned)&STATUS*8)+3; volatile bit nTO @ ((unsigned)&STATUS*8)+4; volatile bit IRP @ ((unsigned)&STATUS*8)+7; volatile bit RP0 @ ((unsigned)&STATUS*8)+5; volatile bit RP1 @ ((unsigned)&STATUS*8)+6; #ifndef _LIB_BUILD volatile union { struct { unsigned C : 1; unsigned DC : 1; unsigned Z : 1; unsigned nPD : 1; unsigned nTO : 1; unsigned RP : 2; unsigned IRP : 1; }; struct { unsigned : 5; unsigned RP0 : 1; unsigned RP1 : 1; }; } STATUSbits @ 0x003; #endif // Register: FSR volatile unsigned char FSR @ 0x004; // bit and bitfield definitions // Register: PORTA volatile unsigned char PORTA @ 0x005; // bit and bitfield definitions volatile bit RA0 @ ((unsigned)&PORTA*8)+0; volatile bit RA1 @ ((unsigned)&PORTA*8)+1; volatile bit RA2 @ ((unsigned)&PORTA*8)+2; volatile bit RA3 @ ((unsigned)&PORTA*8)+3; volatile bit RA4 @ ((unsigned)&PORTA*8)+4; volatile bit RA5 @ ((unsigned)&PORTA*8)+5; #ifndef _LIB_BUILD volatile union { struct { unsigned RA0 : 1; unsigned RA1 : 1; unsigned RA2 : 1; unsigned RA3 : 1; unsigned RA4 : 1; unsigned RA5 : 1; }; } PORTAbits @ 0x005; #endif // Register: PORTB volatile unsigned char PORTB @ 0x006; // bit and bitfield definitions volatile bit RB0 @ ((unsigned)&PORTB*8)+0; volatile bit RB1 @ ((unsigned)&PORTB*8)+1; volatile bit RB2 @ ((unsigned)&PORTB*8)+2; volatile bit RB3 @ ((unsigned)&PORTB*8)+3; volatile bit RB4 @ ((unsigned)&PORTB*8)+4; volatile bit RB5 @ ((unsigned)&PORTB*8)+5; volatile bit RB6 @ ((unsigned)&PORTB*8)+6; volatile bit RB7 @ ((unsigned)&PORTB*8)+7; #ifndef _LIB_BUILD volatile union { struct { unsigned RB0 : 1; unsigned RB1 : 1; unsigned RB2 : 1; unsigned RB3 : 1; unsigned RB4 : 1; unsigned RB5 : 1; unsigned RB6 : 1; unsigned RB7 : 1; }; } PORTBbits @ 0x006; #endif // Register: PORTC volatile unsigned char PORTC @ 0x007; // bit and bitfield definitions volatile bit RC0 @ ((unsigned)&PORTC*8)+0; volatile bit RC1 @ ((unsigned)&PORTC*8)+1; volatile bit RC2 @ ((unsigned)&PORTC*8)+2; volatile bit RC3 @ ((unsigned)&PORTC*8)+3; volatile bit RC4 @ ((unsigned)&PORTC*8)+4; volatile bit RC5 @ ((unsigned)&PORTC*8)+5; volatile bit RC6 @ ((unsigned)&PORTC*8)+6; volatile bit RC7 @ ((unsigned)&PORTC*8)+7; #ifndef _LIB_BUILD volatile union { struct { unsigned RC0 : 1; unsigned RC1 : 1; unsigned RC2 : 1; unsigned RC3 : 1; unsigned RC4 : 1; unsigned RC5 : 1; unsigned RC6 : 1; unsigned RC7 : 1; }; } PORTCbits @ 0x007; #endif // Register: PORTD volatile unsigned char PORTD @ 0x008; // bit and bitfield definitions volatile bit RD0 @ ((unsigned)&PORTD*8)+0; volatile bit RD1 @ ((unsigned)&PORTD*8)+1; volatile bit RD2 @ ((unsigned)&PORTD*8)+2; volatile bit RD3 @ ((unsigned)&PORTD*8)+3; volatile bit RD4 @ ((unsigned)&PORTD*8)+4; volatile bit RD5 @ ((unsigned)&PORTD*8)+5; volatile bit RD6 @ ((unsigned)&PORTD*8)+6; volatile bit RD7 @ ((unsigned)&PORTD*8)+7; #ifndef _LIB_BUILD volatile union { struct { unsigned RD0 : 1; unsigned RD1 : 1; unsigned RD2 : 1; unsigned RD3 : 1; unsigned RD4 : 1; unsigned RD5 : 1; unsigned RD6 : 1; unsigned RD7 : 1; }; } PORTDbits @ 0x008; #endif // Register: PORTE volatile unsigned char PORTE @ 0x009; // bit and bitfield definitions volatile bit RE0 @ ((unsigned)&PORTE*8)+0; volatile bit RE1 @ ((unsigned)&PORTE*8)+1; volatile bit RE2 @ ((unsigned)&PORTE*8)+2; #ifndef _LIB_BUILD volatile union { struct { unsigned RE0 : 1; unsigned RE1 : 1; unsigned RE2 : 1; }; } PORTEbits @ 0x009; #endif // Register: PCLATH volatile unsigned char PCLATH @ 0x00A; // bit and bitfield definitions #ifndef _LIB_BUILD volatile union { struct { unsigned PCLATH : 5; }; } PCLATHbits @ 0x00A; #endif // Register: INTCON volatile unsigned char INTCON @ 0x00B; // bit and bitfield definitions volatile bit RBIF @ ((unsigned)&INTCON*8)+0; volatile bit INTF @ ((unsigned)&INTCON*8)+1; volatile bit TMR0IF @ ((unsigned)&INTCON*8)+2; volatile bit RBIE @ ((unsigned)&INTCON*8)+3; volatile bit INTE @ ((unsigned)&INTCON*8)+4; volatile bit TMR0IE @ ((unsigned)&INTCON*8)+5; volatile bit PEIE @ ((unsigned)&INTCON*8)+6; volatile bit GIE @ ((unsigned)&INTCON*8)+7; volatile bit T0IF @ ((unsigned)&INTCON*8)+2; volatile bit T0IE @ ((unsigned)&INTCON*8)+5; #ifndef _LIB_BUILD volatile union { struct { unsigned RBIF : 1; unsigned INTF : 1; unsigned TMR0IF : 1; unsigned RBIE : 1; unsigned INTE : 1; unsigned TMR0IE : 1; unsigned PEIE : 1; unsigned GIE : 1; }; struct { unsigned : 2; unsigned T0IF : 1; unsigned : 2; unsigned T0IE : 1; }; } INTCONbits @ 0x00B; #endif ... ... ...
Hi Romel,
What is the actual purpose of the code snippet?
Is the one second delay within the for loop for display purposes? Is P2 being displayed on LEDs, etc?
plz help me i m beginner in pic and MPLab.......in the pic 16f877a i use timer0.....and than i use T0CON (timer0 control). the MPLab complier give the :
Error [192] F:\PIC16F877A\MPLab\test_2.c; 10.1 undefined identifier "T0CON"
plz plz help me.!
#include<pic.h>
__CONFIG(0x3F38); //for Internal oscillator
char count;
void interrupt timer0()
{
if(T0IF == 1)
{
T0IF = 0;
count++;
if(count == 15)
{
RA2 ^= 1; //toggle LED
count = 0;
}
}
T0IE = 1; //Disables the TMR0 interrupt
}
void main(void)
{
TMR0 = 0;
OPTION_REG = 0b0111; // set prescaler to timer 0 and 1:256 prescaler..
T0CS = 0; // timer 0 Internal clock source
T0IE = 1; // enable timer 0 interrrupt
GIE =1; // Enable global interrupt
TRISA2 = 0; //set bit 1 of portB as output.
while(1);
}
yes. It's just being displayed on 8 LEDs connected to P2.
Code C - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 void shift_right() { char c; if(P1 == 0x04) { P2 = 0xA0; for(c=0; c<3; c++) { delay_ms(1000); P2 = P2 >> 1; } } }
Code C - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 void main(void) { unsigned char sP1; // Shadow Copy of P1 unsigned char sP2; // Shadow Copy of P2 ... ... ... void shift_right() { unsigned char c; if(sP1 == 0x04) { sP2 = 0xA0; P2 = sP2; for(c=0; c<3; c++) { delay_ms(1000); sP2 = sP2 >> 1; P2 = sP2; } } } }
The technique of using shadow registers, prevents unforeseen changes in the state of a volatile register, e.g. PORT2, from corrupting the calculation or routine's outcome.
void shift_right()
{
[COLOR="#FF0000"]char c; // unsigned char c; A good policy[/COLOR]
if(P1 == 0x04)
{
P2 = 0xA0;
for(c=0; c<3; c++)
{
delay_ms(1000);
P2 = P2 >> 1;
}
}
}
Code C - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 /* Characteristics of integral types */ #define CHAR_BIT 8 /* bits per char */ #define CHAR_MAX 127 /* max value of a char */ #define CHAR_MIN -128 /* min value of a char */ #define SCHAR_MAX CHAR_MAX /* chars are signed */ #define SCHAR_MIN CHAR_MIN #define UCHAR_MAX 255 /* max value of an unsigned char */ #define SHRT_MAX 32767 /* max value of a short */ #define SHRT_MIN (int)-32768 /* min value of a short */ #define USHRT_MAX 65535 /* max value of an unsigned short */ #define INT_MAX 32767 /* max value of an int */ #define INT_MIN (int)-32768 /* min value of an int */ #define UINT_MAX 65535 /* max value of an unsigned int */ #define SHRTLONG_MAX 8388607 /* max value of short long */ #define SHRTLONG_MIN (short long)-8388608 /* min value of a short long */ #define USHRTLONG_MAX 16777215 /* max value of an unsigned short long */ #define LONG_MAX 2147483647 /* max value of long */ #define LONG_MIN (long)-2147483648 /* min value of a long */ #define ULONG_MAX 4294967295 /* max value of an unsigned long */
void main()
{
//working code
unsigned char i;
P2=0x00;
while(1)
{
delay_ms(1000);
P2 = 0x00; // to clear the previous value of port
i=i>>1;
if(i==0)
i=0x80;
P2=P2|i;
}
}
void main()
{
//problematic code. hehe
signed char i;
P2=0x00;
while(1)
{
delay_ms(1000);
P2 = 0x00;
i=i>>1;
if(i==0)
i=0x80;
P2=P2|i;
}
}
A.5.5 The result of a right shift of a negative-valued signed integral type (6.3.7)
The right shift operator sign extends signed values. Thus an object with the signed int value 0x0124 shifted right one bit will yield the value 0x0092 and the value 0x8024 shifted right one bit will yield the value 0xC012. Right shifts of unsigned integral values always clear the most significant bit of the result. Left shifts (<< operator), signed or unsigned, always clear the least significant bit of the result.
you have always a reference as a prof.. hehe
by the way did you read all this things up before?
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