Phd Topic in Backend Physical design (synthesis, PnR)

shobhit · Feb 2, 2022

Hi,

Can any one please suggest good PhD topic ASIC design
Iam Backend Engineer so looking for Synthesis/STA/Physical Design

ThisIsNotSam · Feb 10, 2022

first, talk to your supervisor. topic decisions are often linked to the availability of funding

classical CAD is still an active topic in select universities in US and Japan. To this day, there are still researchers developing routers and placers. you need to have a very good grasp of C++ and data structures.
if you want to do something a bit more applied, there are many opportunities in hardware security and the links with physical synthesis.

Trent_N · Apr 2, 2022

I have always wanted a good synthesis tool that can create a latch based design from code that was written to use Flip Flops. There are some performance benefits of a latched based design, but not enough tools to support this type of design.
Example of a latch based design that is used to increase the frequency and lower the power of a 2 stage piped design.

always @(posedge clk)
y0 <= a_in * b_in;

always @(posedge clk)
x0 <= (y0 & c_in) | (d_in & f_in);

// -----------------------------------------------------
// latch design (using clk_div2, a clock created using divided by 2 of clk)
// the logic is duplicated. There is a silicon cost for the area of the 2 multipliers, and 2 is needed to keep the pipelined feature from the code. Always a trade off, some speed for 2X the silicon area.

always @(*)
if (!clk_div2) y0_p0 <= a_in * b_in;

always @(*)
if (clk_div2) y0_p1 <= a_in * b_in;

always @(*)
if (clk_div2) x0_p1 <= (y0_p0 & c_in) | (d_in & f_in);

always @(*)
if (!clk_div2) x0_p0 <= (y0_p1 & c_in) | (d_in & f_in);

// The example above shows how duplicate logic is created to generate the y0 and x0 signals. This is a quick example, the a_in, b_in, c_in, d_in, and f_in signals should be duplicated the same as for y0 and x0 but I tried to keep this example short.

// The clock speed can be increased because or the time borrowed by the multiplier. And latches are faster than Flip Flops, and a LC resonate clock can be used.

Trent_N · Apr 2, 2022

Another idea, I have a lot of them.

Create a logic simulator that can run backward and forward in time. Silicon debug is sometimes very difficult and a simulator that can take the output values captured with a logic analyzer and can simulate backward to find the internal logic states.

Example:

Design

always @(posedge clk)
counter <= counter + 1;

assign y_out = counter == 9;

Output captured from a logic analyzer

y_out ...... 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

counter . 0 1 2 3 4 5 6 7 8 9 A B C D E F

The simulator will initialize the counter to 9 when the (y_out == 1).
The simulator will run backward to determine the earlier state of the counter 8-7-6-5-4-3-2-1-0 and will run forward to determine the later state of the counter A-B-C-D-E-F

ThisIsNotSam · Apr 2, 2022

Trent_N said:
I have always wanted a good synthesis tool that can create a latch based design from code that was written to use Flip Flops. There are some performance benefits of a latched based design, but not enough tools to support this type of design.
Example of a latch based design that is used to increase the frequency and lower the power of a 2 stage piped design.

always @(posedge clk)
y0 <= a_in * b_in;

always @(posedge clk)
x0 <= (y0 & c_in) | (d_in & f_in);

// -----------------------------------------------------
// latch design (using clk_div2, a clock created using divided by 2 of clk)
// the logic is duplicated. There is a silicon cost for the area of the 2 multipliers, and 2 is needed to keep the pipelined feature from the code. Always a trade off, some speed for 2X the silicon area.

always @(*)
if (!clk_div2) y0_p0 <= a_in * b_in;

always @(*)
if (clk_div2) y0_p1 <= a_in * b_in;

always @(*)
if (clk_div2) x0_p1 <= (y0_p0 & c_in) | (d_in & f_in);

always @(*)
if (!clk_div2) x0_p0 <= (y0_p1 & c_in) | (d_in & f_in);

// The example above shows how duplicate logic is created to generate the y0 and x0 signals. This is a quick example, the a_in, b_in, c_in, d_in, and f_in signals should be duplicated the same as for y0 and x0 but I tried to keep this example short.

// The clock speed can be increased because or the time borrowed by the multiplier. And latches are faster than Flip Flops, and a LC resonate clock can be used.

this is very interesting stuff and I suspect it was tried (and dropped) some 2 decades ago. other than some super custom datapath, the recommendation is always to avoid latches. for the case you mention above, a good engineer could do it by hand without tool support. this guy would be really earning his salary, so to say.

in a previous lifetime I did design with latches using custom scripts that would just replace flops directly at the netlist. it works fine, the STA captures the intent perfectly. but for sure some trade-offs are left unexplored this way.

Trent_N · Apr 2, 2022

ThisIsNotSam said:
this is very interesting stuff and I suspect it was tried (and dropped) some 2 decades ago. other than some super custom datapath, the recommendation is always to avoid latches. for the case you mention above, a good engineer could do it by hand without tool support. this guy would be really earning his salary, so to say.

in a previous lifetime I did design with latches using custom scripts that would just replace flops directly at the netlist. it works fine, the STA captures the intent perfectly. but for sure some trade-offs are left unexplored this way.

Thanks, I use latches for the high speed logic only when needed. Flip Flops are easier. But, you get paid more when you design fast logic.

Trent_N · Apr 2, 2022

One more on my wish list,
I designed standard cells and like a very large library. Large complex gates can be used in some parts of your design to save power and speed up your logic. The problem with a large library is the creation and maintenance is hard.
An Example cell : 2 stage cell (First stage : 5 input AndOr gate, Second stage : 2 input Nand gate with one of the inputs connected to the output of the AndOr gate.
This is a combination gate the would seldom be used except for some unique design that needed the speed and power of this gate.

The idea is for the synthesis tool to have the option to use a standard cell that has not yet been created, or the PnR tool that is able to modify the gate design and create new standard cells when needed.

There would need to be software that will auto layout a standard cell and auto simulate and characterize the standard cell.

This is a lot to ask I know. I do a lot of custom logic and I am always looking for tools that can match the performance faster than by hand.

Phd Topic in Backend Physical design (synthesis, PnR)

shobhit

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ThisIsNotSam

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Trent_N

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Trent_N

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ThisIsNotSam

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Trent_N

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Phd Topic in Backend Physical design (synthesis, PnR)

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