phase shift in 5stage ring VCO

[pnanda65675]

i hav simulated a 5stage single ended ring VCO. Gettin Td= 10.8ns, Fosc=92.5Mhz. But as per theory a 5 stage ring should give abt 36'degree of phase shift each. Can ny1 tel me how to simulate n c the phase shift using cadence. Becuz for VCO we cant put a pulse at the input, since VCO is feedback frm output to te input. Thanks in advance.....

 

[Vamsi Mocherla]

Since it is a 5 stage VCO, plot the output after two consecutive stages. You should almost notice a 36° phase shift after the waveform settles. There will be some phase error of course. If you are seeing a sine wave, then , you can calculate the value of outputs at a given time. Then apply it to a sine function A.Sin(ωt+Φ) and get the corresponding phase difference.

I hope that I am clear.......

 

[pnanda65675]

Thanks Vamsi...But im quite vague in measuring the phase shift..is tat i dnt need 2 do ac analysis 2 get a phase shift ? By wat u meant, its juz need 2 c te transient output if im not mistaken....N as wat u said im seeing the sin wave but how u calculate phase frm tat...as i knew i can calculate the Td(time delay) frm te output n convert it to Frequency...wit tis i'd enclosed te wave tat produced in te 2stage output.Im still not clear enugh....

 

[Vamsi Mocherla]

Dear pnanda65675,

Of course you can do ac analysis and get the phase shift. But that would be confusing for you are making the notice in frequency domain. My idea was since you will be doing a transient analysis, you can take the value of the output of the two stages at any time, "t" and then do a Sine Inverse on them. Since, your wave function is A.Sin(ωt + Φ), and A, ω, t are common to both the waves, when you take the sine inverse function, the difference in each values give the phase shift.

I hope that I am clear.............

 

[pnanda65675]

Thank you very much Mr. Vamsi Mocherla...i'd realized te phase shift in 5stage ring osc.

Added after 1 hours 5 minutes:

Mr. Vamsi... im actually designin a vco at 3.5GHz using CMOS 0.18um IBM process.After sum research i'd decide 2 use a 4 stage diff ring architecture but te prb tat i hav now is te delay cell inside te ring.I cant analysed te general delay cell tat given in behzad razavi's book ( pg 513),as stated in te book te 2 symmetrical active load must b kept in TRIODE region(to make te pmos act as a variable resistor) & te rest in saturation region. as we knw tat te output is feedback to te input( i fixed te same volt at both Vin & Vout node ). Vcont & Vbias as 1V & 0.6V . N te tail current is set as 1.5mA, n a rough calculation of my power dissipation must b within 1-20mW. But after obey all te condition te cct doesnt seems like oscillate. I cant find te reason y it nvr oscillate. I'd enclosed te cct n te waveform below for ur consideration. R Mr.Vamsi do u hav ny other suggestion for delay cell r acrhitec. Thanks alot 4 ur previous help. hope u guide me...