Romeo shashi
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Hi,
I would like to simulate fullbridge DC DC converter with the following parameters in LT spice with 95% efficiency. Here Iam doing synchronous rectification on the secondary side the delay between SA,SB and SC,SD is 50ns and overlap between M5&M6 is 100ns with dutycycle of 45%. but Iam getting efficiency around 85% (Pi=1887&Po=1608) but Iam aiming for 3k output power what parameters i can change in the ckt to get required power? how much duty is efficient to achieve ZVS with synch-rectification?
Please find my simulation pics in the attachments.
my specifications are:
i/p vol - 400v
o/p voltage - 28v
o/p power - 3kw
Frequency - 1mhz
I would like to simulate fullbridge DC DC converter with the following parameters in LT spice with 95% efficiency. Here Iam doing synchronous rectification on the secondary side the delay between SA,SB and SC,SD is 50ns and overlap between M5&M6 is 100ns with dutycycle of 45%. but Iam getting efficiency around 85% (Pi=1887&Po=1608) but Iam aiming for 3k output power what parameters i can change in the ckt to get required power? how much duty is efficient to achieve ZVS with synch-rectification?
Please find my simulation pics in the attachments.
my specifications are:
i/p vol - 400v
o/p voltage - 28v
o/p power - 3kw
Frequency - 1mhz