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https://www.infineon.com/dgdl/Infin...D.pdf?fileId=db3a30433f9a93b7013f9f582ddb1fd9
(ZVS Phase shift full bridge CFD2 optimized design)
The above app note, on Phase shift full bridge converters, at the bottom of page 18, says…………….
“For safety reasons the delay time must be adjusted at the minimum load at which the synchronous rectification is activated. Otherwise there is a risk of destruction of the parts when decreasing the load due to an overlap of VGS and VDS”
Why should the FETs be destroyed by the overlap of VGS and VDS?…..I mean, overlap of VGS and VDS occurs in every single hard-switched SMPS in the world, and it doesn’t result in “destruction” of the FETs………………..so why in a phase shift full bridge converter should this overlap result in destruction?
(ZVS Phase shift full bridge CFD2 optimized design)
The above app note, on Phase shift full bridge converters, at the bottom of page 18, says…………….
“For safety reasons the delay time must be adjusted at the minimum load at which the synchronous rectification is activated. Otherwise there is a risk of destruction of the parts when decreasing the load due to an overlap of VGS and VDS”
Why should the FETs be destroyed by the overlap of VGS and VDS?…..I mean, overlap of VGS and VDS occurs in every single hard-switched SMPS in the world, and it doesn’t result in “destruction” of the FETs………………..so why in a phase shift full bridge converter should this overlap result in destruction?