phase noise to jitter in verilogA

[nandu]

vco + noise + veriloga

Hi

I have simulated pss and pnoise of a VCO and have extracted a table of its phase noise vs frequency in dBc/Hz. Now I need to estimate how much jitter this contributes to a PLL loop. For this I have a PLL loop with ideal elements, but I want the ideal VCO block to take the phase noise table of the actual VCO as its input and produce the corresponding jitter at its output. How do I do it? Can I do it using VerilogA?

 

[mr_chip]

Make a simple freq domain model including noise transfer functions from VCO, prescaler, PFD/CP, SDM (if any) to PLL output. You'll get an estimate of PLL output phase noise. Then just intergrate - you'll get your jitter.