phase noise simulation of the frequency divider in a PLL

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yfluo2004

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Hi,

I am simulating the phase noise contribution of each component in a PLL and met a problem about the phase noise simulation of the frequency divider.

I checked the website, many papers talked about how to modeling the phase noise of the frequency divider, but seldom talked about how to extract the parameters in their phase noise model from the Cadence simulation results and how to simulate the frequency divider phase noise in Cadence.

Does anybody know how to simulate the phase noise of the frequency divider in Cadence?

Thanks a lot.

YLuo
 

I don't see the difficulty in doing this., Or am I misinterpreting the question?
If the input frequency is fvco and the output is fvco/8 (say), pss will settle at fvco/8. You have to get the phase noise from input to output with refsideband=0.
You have to provide an ideal reference clock to get the inherent noise from the divider. This can be translated back to the VCO output by multiplying by the divide ratio to get the output noise (if you are summing the noise source at the output).
 

Hi, saro_k_82,

Thank you for your answer. I think your solution is for the divider composed by D flip-flop which is formed by several /2 divider. If I use a prescaler to form a programmable divider. Will the method be the same to simulate the phase noise of this kind of divider?

Thank you.

YLuo
 

This solution works for any black box that takes a clock and gives out a divided clock.
It is applicable to your prescaler divider as well.
 

Hi, saro_k_82,

Ok, I will try that. And one more question, have you ever met the problem of "Insufficient memory available" during the divider phase noise simulation?

Currently I am simulating a prescaler divider with divide factor 125 and the ideal input signal at 10GHz. The fundamental frequency was set to 80MHz and the harmonics was set to only 1, but it still generates the "insufficient memory" error. Do you have any ideas how to solve this problem?

Thank you.

YLuo
 

yfluo2004 said:
... it still generates the "insufficient memory" error. Do you have any ideas how to solve this problem?
Click to expand...
Never had this error message from Spectre (with 4GB RAM); it uses memory frugally and can dynamically assign it. If, however, you should actually run short of memory, you could define an appropriate swapfile size, s. the Spectre Circuit Simulator Reference, p. 43. This is also possible for other simulators, like Spice, SpiceS, Hspice, Eldo, AFAIR. Of course this affects the simulator to run more slowly.
 

Exactly., as erikl said, a swap file helps. I do it everytime I run a pss.
 

Thanks, Erikl. Now I have no problem with that after set a swapfile.

YLuo
 


Hi YLuo,

Have you an idea how can i simulate the phase noise contribution of each component in a PLL using MATLAB (.m) files or simulink model.

Thank a lot.
 

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