Phase margin plot of LDO

[promach]

For this LDO circuit design at https://github.com/promach/LDO/tree/development ,

1) which exact circuit node(s) contributes to the zeroes near 1MHz after removing CL ?

2) If I remove "AC 1" from Vref, why the whole bode plot becomes erratic ?

 

[d123]

Hi,

1) At a guess, the LC feedback, if that's a complex conjugate pole double-peaking at around 10MHz.

At 0dB there is rising phase margin, I think that is undesirable, afaik, going on SMPS control loops. Shouldn't PM be positive at 0dB and gain negative at PM = 0?

Placing an RC from feedback to EA Vout makes a zero. A parallel RC from Vout to feedback pin is another zero.

...No idea, maybe setting poles lower down and wider apart like a band pass (e.g. 100kHz and 100MHz) could improve response.

Pole = series RC from Vout to feedback pin
= parallel RC from feedback pin to EA Vout pin/node.


2) No idea, maybe sim tool needs a little complementary ripple to square its sums properly...

 

[promach]

Placing an RC from feedback to EA Vout makes a zero. A parallel RC from Vout to feedback pin is another zero.

Where did you find parallel RC in my LDO circuit ?

Pole = series RC from Vout to feedback pin
= parallel RC from feedback pin to EA Vout pin/node.

What did you exactly mean by EA Vout pin/node ?
How is EA Vout different from Vout ?

 

[d123]

Hi,

Obviously, I don't see any but as you appear to want to improve stability, those are my suggestions as to what might help.

To me, Vout is the pass device output voltage and EA Vout is the output voltage from the EA driving the pass device.

 

[promach]

But what did you exactly mean by EA ?
Which pass device , as in which mosfet , is it M20 ?

 

[d123]

Hi,

Error Amplifier. If M20 is what passes Vin to Vout and is controlled by the feedback section, yes.

M22 is a resistor, is it? If not, what does it do, please? I assume it is a resistor as I know they are sometimes used in series with a Miller capacitor for stability.

I read that (in SMPS loops) phase rising after 0dB point is not desirable, especially close to 0dB crossover, as it indicates instability. You can allegedly guage stability and therefore an approximation of phase margin by amount of overshoot and ringing with a load step.

You'll know if any of the things I've said actually apply to an LDO circuit or not. I think some of it should. Another amateur guess is that you have H(s), feedback and error amplifier, and G(s), a MOSFET power stage in this case, so presumably a T(s). Linear and switching look similar to me in that both require a power stage, a feedback network of some kind, a controlling device and a way to implement stability. Linear regulation gets away with swamped output capacitance and sometimes a parallel RC network across top feedback resistor, I don't know of other techniques besides implementing type 1, 2, or 3 compensation to boost stability and improve transient response, especially in IC design...

Curious so I can learn - does the LDO need to be stable at high frequencies or is it like off-the-shelf IC ones aimed at DC input that may not go much further than coping with e.g. 10kHz bandwidth stable response?

You presumably know a lot more about this stuff than I do as you are able to do transistor-level design.

 

[FvM]

What should be the purpose of having two AC sources in the simulation circuit? Looks like a copy-and-past error from PSRR simulation.

You have two transistors (M14 and M22) without DC path. Hard to believe that they have a useful function in your circuit. What's the idea behind this topology? In case they are intended as buffers, you forgot respective loads, e.g. current sources.

I just noticed that you have posted the strange feedback topology already in your previous thread https://www.edaboard.com/threads/ld...-in-the-event-of-a-sudden-load-change.390217/

 

[promach]

@FvM

M14 and M22 are for Miller Compensation

 

[FvM]

Yes, compensation buffer was my guess. However a transistor buffer can't work without quiescent current. These transistors in cut-off are probably the unwanted feedforward paths you are looking for.

 

[promach]

These transistors in cut-off are probably the unwanted feedforward paths you are looking for.

Even after I had removed M14 and M22 and their respective miller capacitors, the zeroes at 1MHz are still there......

 

[FvM]

The compensation capacitors are apparently too small to have significant effect on the loop gain.

I don't see zeros but a relative low frequent pole in the input stage resulting in insufficient phase margin. Reason is the low current mirror transistors M11 and M17. I believe the whole design is flawed.

 

[promach]

@FvM

The bode plot shown above may not reflect actual result if I am not wrong. There are 2 AC stimulus in the test circuit.

See https://www.edaboard.com/threads/mi...middlebrooks-general-feedback-theorem.393450/

 

[promach]

If I use the middlebrook method as described in The Designer's Guide to SPICE and Spectre® (The Designer's Guide Book Series)

 

[FvM]

It's a good idea to use Middlebrook's methode. But why do you still have two AC sources which makes the results useless?

 

[promach]

@FvM Middlebrook method requires an AC source "AC 1" on the feedback path.

See https://github.com/Ribster/LTSpice/issues/1

 

[FvM]

Middlebrook method requires an AC source "AC 1" on the feedback path.

Sure, but no second AC source in the power supply. You can either measure PSSR or loop gain, but not both at the same time.

 

[promach]

but no second AC source in the power supply

I have just removed the second AC source. The test circuit is now updated at this link here

 

[FvM]

Plausible loop gain frequency response, but insufficient phase margin, as you surely recognize.

 

[FvM]

A major difference to previous simulation setups is missing output capacitor. One would define useful load conditions before starting to change the compensation.

 

[promach]

Plausible loop gain frequency response, but insufficient phase margin, as you surely recognize.

@FvM I suppose phase margin is defined as the distance away from 180 degrees ???