phase margin of voltage regulator in the nonvolatile memory

[carlson]

Hi all,
Normally, the phase margin is larger than 45 degree. But I heart that the PM of the voltage regulator in the nonvolatile memory can less than 45 degree from my leader. I don't know it's true.
If you are the nonvolatile memory designer ,Can you give me the answer ?

 

[Btrend]

Re: phase margin of voltage regulator in the nonvolatile me

The larger PM , the more stable of your regulator, and less ringing when dynamic load is asserted. And real chip have many parasitics which will probably generate
extra pole around ur unit gain frequency, these extra poles will degrade ur PM.
so choose PM > 45 or PM > 60 are prefered to make ur design more robust.

I think u should challenge him why he designed PM < 45 ?
If he can design PM > 45, why he want to reduce PM to less than 45 ?
maybe he had other reasons ...!?

 

[carlson]

Re: phase margin of voltage regulator in the nonvolatile me

Thanks!
I think that PM must be larger than 45 degree.

 

[elbadry]

Re: phase margin of voltage regulator in the nonvolatile me

I think that the 45 degree is used to give a margin against process variations and/or parasitics + un calculated loads that may affect u after production

Theoritically speaking, any PM greater than zero is stable. However, the time it takes the output to get stable will decrease as PM increases

 

[scottieman]

Re: phase margin of voltage regulator in the nonvolatile me

Theoritically speaking, any PM greater than zero is stable. However, the time it takes the output to get stable will decrease as PM increases

Totally, agree with "elbadry"
Some input from me is that voltage regulator in NVM application is just to provide high enough voltage for program and erase, the voltage regulator (usually a charge pump) is in open loop with some over-voltage protection only. So, if it is the situation in your case, what is the importance of PM?

Hope it helps
Scottie

 

[carlson]

Re: phase margin of voltage regulator in the nonvolatile me

Thanks for all of you replies!
And I have a new questions:
If the precise voltage is be need , the LDO architecture would be used. Is it important for this applications.

 

[scottieman]

Re: phase margin of voltage regulator in the nonvolatile me

Thanks for all of you replies!
And I have a new questions:
If the precise voltage is be need , the LDO architecture would be used. Is it important for this applications.

I would like to say, if precision voltage is needed, begative feedback control is required no matter what types of voltage converters you are using.

 

[yanzushu]

Re: phase margin of voltage regulator in the nonvolatile me

For low cermic capacitor LDOs, it usually difficult to keep PM larger than 45 degrees under all load conditions. eg, from 0mA to 150mA