phase frequency detector

you could do this with a multiplier, but not sure you can get 0.02% accuracy.

Hi,

Where and how did you search?
In every PLL there is a phase detector. It uses twodigital signals and an XOR to "compare" them.

All you have to do is to generate a square wave from your sine inputs. --> Comparator

For sure there is some additonal work to get 0..10V for 0..360°... but since you showed no effort on your own....

Klaus

Surely 0.02% accuracy? Not linearity, precision...
0.02% is 0.072° or 4us (if my mind calculation is right)

Due to discontinuity, circuit doesn't work around 0°. If 0/360° is within expected measurement range, you'll need at least extra logic to get a readable display.

Other problem, specified accuracy will require heavy input band pass filtering for real input signals. Otherwise a small amount of noise and harmonics would kill it.

Phase detector 2 & 3 in the CD4046 have a 360 degree range :



Regards, Dana.

Phase detectors work by time-of-arrival and give a yes/no, up/down
output. You're asking for a phase -measurement-.

If you know for a fact that it's 50Hz for both then your solution is a
bit more straightforward (though likely not as cheap or easy as you
would like).

Suppose you took an available PLL and put its VCO through a
12-bit counter to feed back. Now start the count with phase_ref
and stop the count & read out with phase_meas. Unpack the
code to degrees.

Phase detectors generally rate by max frequency but that does
not mean you can't use them lower. Just pick one that isn't a
pain to interface.

I guess VCO input is proportional to phase difference. Can this not be used as a direct readout without going through VCO. Because I am not looking for a phase lock

curious_mind said:

I guess VCO input is proportional to phase difference. Can this not be used as a direct readout without going through VCO.

Click to expand...

No and no. VCO input is proportional to frequency. dick_freebird is suggesting a digital phase difference measurement method, using a PLL reference clock. If you don't like this approach, you should look closer at the phase detectors discussed by danadakk and other solutions.

Hi,

No and no?

To avoid confusion, let's call
* the "voltage controlled oscillator" circuit --> "VCO"
* the VCO analog input to control the frequency --> V_tune

In so far V_tune is (like FvM writes) the frequency proportional input to the VCO.
On the other hand this signal is generated from the phase comparator, and thus (usually RC low pass filtered) also represents the phase shift between the reference clock and the VCO clock (both may be divided).
The whole PLL uses the "phase shift" to adjust the "frequency" as one single signal.

For the PLL loop (regulation and stability calculation) the "integrating part" of the loopfilter is of interest. But still the DC part shows the phase difference.

Or the other way round: for the VCO output to generate a useful frequency, the V_tune is usually not zero.
Not zero, also means the phase_shift is not zero. (Still might be rather small).

Remainig phase shift can only be zeroed if a true integrator is used as loop filter.
Then the integrator input is considered to be zero (zero phase shift), but still the integrator output (V_tune) is non zero (non zero frequency).

("Non zero frequency" ... for a VCO ... here is meant as "the lowest possible output frequency")

Klaus

Vtune may be proportional to frequency offset but phase is
probably too fine to look at without disturbing. And you don't
get to know the scale and offset of that "k_V" of the VCO
(unless you spend a lot for that tolerance & data-set). The
stated tolerance wants more than simply "proportional".

Ok. Could you suggest a workaround. I haven't tested CD4046. (i am yet to buy and test it). Do you mean that type3 phase detector output do not generate analog outputs linearly and proportionally for the phase/frequency change?

Hi,

1) CD4046 is a complete PLL. Your initial question is about phase detector only. So what do you really need?
2) My 4046 datasheet shows only type1 and type2 phase detectors. But not type3. Maybe a link to your datsheet can avoid confusion.

Klaus

Most LDO regulators are around 1% accurate and sensitive to temperature and load. Unless you "ovenize" the circuit and have significant analog design experience, you will never achieve 0.02%. or 1 part in 5,000 with SNR = 80 dB for interference free.

Therefore you must consider what Dick_freebird has suggested. with at least a 12 bit counter using 50 Hz * 5000 = 250 kHz time interval (T.I.) counter to measure phase. You still need 80 dB SNR on both signals and a design spec on how to verify this error.The zero crossing threshold or offset must also be regulated within 80 dB SNR for the comparator.

Thus no VCO, mixer or PLL. Just a uC with a TI counter and fast enough clock and adequate resolution.

KlausST said:

Hi,

1) CD4046 is a complete PLL. Your initial question is about phase detector only. So what do you really need?
2) My 4046 datasheet shows only type1 and type2 phase detectors. But not type3. Maybe a link to your datsheet can avoid confusion.

Klaus

Click to expand...

Post 5 has link to datasheet with Type III phase detector,



Regards, Dana.

danadakk said:

Post 5 has link to datasheet with Type III phase detector,

View attachment 183118

Regards, Dana.

Click to expand...

have you ever seen 70~80 dB SNR out of PC2 or PC3? I used the T.I. method in 1975 using discrete counters for VLF navigation. At that time our Manitoba Hydro 60 Hz was geostationary synchronized too so it was very stable compared to my 1e-12 OCXO HP counter. in fact I had to add white noise to avoid error and average.

Hi,

danadakk said:

Post 5 has link to datasheet with Type III phase detector,

Click to expand...

Thanks. Indeed your post lead me to the correct information.

(Being picky on the link: It´s not a datasheet, and not for 4046 but 4046A)
Thus I did not find the information in the 4046 datasheet. :-( ...

50% my bad?

***
in the document of post#5:
there is a diagram for PC2 shoing V_DEM vs Phi. Phi in the range of -360° to +360°. I wonder how they differ between -180° and +180°. For me the waveform is identical.

But more to the topic:
As written in the document, the type3 phase comparator is just an RS Flip Flop.
So still my 1st question of post#12 applies: Does the OP need an RS Flip Flop or a complete PLL?

And a comment about accuracy: The low pass filtered output of the phase comparator is 0 to VCC. So to display the value with an accuracy of 0.02% you can´t go with VCC as reference. I don´t even think the accuracy is possible ratiometric style because of the output impedance of the comparator´and the expectable fluctuation of VCC.
So the better approach is either a digital decoder, or using a good voltage reference and an analog witch controlled by the comparator output.

Klaus

You cannot use PC2 or PC3 for low phase noise PLL as there is a deadtime at 0 deg sync and this small hysteresis is a source of random noise and also amplifying existing noise. Whereas it is excellent for unlimited frequency error capture range, But you do not want or need a PLL rather just a linear phase error value and a T.I. counter gives the resolution and digital result, one expects.
If my assumption is wrong and an analog linear phase error voltage is required, then better specs are needed to define range, stability spectrum and how carry out or cycle slip is handled.

When you define how to achieve better than 0.02% accuracy on your LDO which affects the gain error on an XOR type I PD, you can consider this for an analog solution. But seriously a 10 ppm Xtal on a PIC processor could be your solution with a precision noise rejection filter and precision comparator.

Use BCD decade counters with phase measured in uS rather than deg.
Although obsolete, you can buy a lifetime supply of ICM7216DIPI which can support up to 8 DIGIT LED's

KlausST said:

Hi,

Thanks. Indeed your post lead me to the correct information.

(Being picky on the link: It´s not a datasheet, and not for 4046 but 4046A)
Thus I did not find the information in the 4046 datasheet. :-( ...

50% my bad?

***
in the document of post#5:
there is a diagram for PC2 shoing V_DEM vs Phi. Phi in the range of -360° to +360°. I wonder how they differ between -180° and +180°. For me the waveform is identical.

But more to the topic:
As written in the document, the type3 phase comparator is just an RS Flip Flop.
So still my 1st question of post#12 applies: Does the OP need an RS Flip Flop or a complete PLL?

And a comment about accuracy: The low pass filtered output of the phase comparator is 0 to VCC. So to display the value with an accuracy of 0.02% you can´t go with VCC as reference. I don´t even think the accuracy is possible ratiometric style because of the output impedance of the comparator´and the expectable fluctuation of VCC.
So the better approach is either a digital decoder, or using a good voltage reference and an analog witch controlled by the comparator output.

Klaus

Click to expand...

The deadtime phase error Tony mentioned in several ap notes on phase comparators, which limits SNR
as he previously pointed out.

Regarding Vcc as reference, just use a precision Vref to power parts with that problem. Obviously
any load attached to output has to be buffered, eg. filter, to maintain the Vref driven accuracy at'
output.


Regards, Dana.

Hi,

danadakk said:

Regarding Vcc as reference, just use a precision Vref to power parts with that problem. Obviously
any load attached to output has to be buffered, eg. filter, to maintain the Vref driven accuracy at'
output.

Click to expand...

I´ve never done this approach before. But 0.02% accuracy is hard to achieve. Hard for a reference, and even harder if the reference is used as power supply and additionally if you rely on the output of a digital logic chip to go to exactly to 0V and VCC (within 0.02% error) .
I wouldn´t rely on it.

The approach with an analog switch is much more accurate. You have predictable timing, predicatable (specified) resistance ... and the tolerance errors of R and C of the low pass filter don´t cause accuracy errors.

Klaus

5V Vrefs. +/- .01%


As far as Vout = GND or VDD, no current drawn thru its Rdson = 0 Volts drop.

And we are talking about 15-16 bit resolution done now in CMOS (processors now doing 24 bits) :




Regards, Dana.