phase difference between the output of a T Flip flop and and clock applied to it

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What is phase difference between the output of a T Flip flop and and clock signal applied to it,when the input to the flip flop is high.
 

Let the clock frequency applied to the flip flop is 1Mhz and a high input is applied to the clock we know that the output frequency of the T-ff would be 0.5Mhz but what is the relation between the relation between clock signal applied and the o/p signal in terms of phase?
What would be the phase difference between them?
 

Your question is quite confusing but I think as the frequency of output is exact half of the clock when i/p is 1 so it will depend on the logic level of the clock...you didn't mention whether the FF is a rising edge or falling edge triggered one...
 

Do you want to know clock to output delay of a trigger?
 

Crazy_Engineer said:
Your question is quite confusing but I think as the frequency of output is exact half of the clock when i/p is 1 so it will depend on the logic level of the clock...you didn't mention whether the FF is a rising edge or falling edge triggered one...
Click to expand...

what would be the phase if the ff is raising edge type
 

I think you are asking the the time between clock rising edge to output toggle. If clock rising edge occurs at t=t_0, output toggles at time t=t_0+t_delay. What is t_delay?
It really depends on the model of TFF you are using. If you are using a discrete IC, check the datasheet, if you are using an FPGA do a post-routing simulation.
 


I want to know the phase difference or phase angle b/w clock and T o/p

1 cycle in O/p of T flipflop is equal to two clock cycles of clock.What can we infer about phase by this.

I need answer badly to this question.This answer is highly important to me.somebody please respond with correct answer.
 
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