PGS Layout- Novel Architecture

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hrkhari

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Hi Guys:

As shown in Figure below, What is meant by Metal-1 strapped to the silicided poly. How does this strapped architecture looks like?. Thanks in advance

Rgds
 

Problems:

1. Increase capacitance and therefore reduces maximum Q

2. Does not solve short circuit currents in the substrate

3. Noise isolation could also be done with NWELL
 

Inductors simply take up too much area upto 10 GHz and below. I have seen SerDes circuits where they are now using SAW filters externally to clean up the output of a lousy onchip oscillator. Lousy oscillators take less power which is an attractive feature. If you are shooting for a high-Q system, look no further.

These SAW resonators are 20c each. They used to be $20 each in 1995; and the Q is simply not a problem anymore.

For monolithic high-Q solutions, there are Cu inductors (adds an extra step) and there are MEMs options (this increases area).

If anyone has designed and tested an inductor for a 65nm process, please share your experiences.
 

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