Persistent Verilog-A variables for co-simulation with H-SPICE

Status
Not open for further replies.

pizzadoe

Newbie level 1
Joined
Aug 13, 2013
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Visit site
Activity points
7
I'm trying to write verilog models to implement optical components in SPICE simulations, using HSPICE as the simulator. The issue is these models will require variables to persist over multiple steps in the SPICE simulation, and it currently seems that H-SPICE instantiates and destroys the model at each time step, so the variables are lost. Is there any simple way to make this data persistent?
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…