Persistent Glitches in ALU Simulation Despite Timing Adjustments – Need Advice

[rayan_ee]

Hello everyone,

I'm working on simulating a simple ALU using logic gates and a multiplexer in a schematic-based environment. I keep encountering glitches (spikes) in the output during transitions, and I've tried several adjustments, but nothing seems to fully resolve the issue. The output has spikes during transitions, as seen in the simulation waveform. These glitches seem to occur between stable states of the output.

Circuit Overview:​

• The ALU consists of basic gates (AND, OR), a Full Adder and a 4:1 multiplexer (MUX).
• Inputs are typical logic signals: A, B, Cin (carry-in).
• Control signals are S1 and S0 for MUX selection.

Inputs and Stimuli:​

Initially, I used:

• Delay time: 100ps and later 500ps
• Rise/Fall time: 100ps and later 500ps
• Period: 20ns

the below waveforms shows output from setting stimuli to 500ps

 

[dick_freebird]

Charge injection, what problem does this cause?

 

[FvM]

Glitches are normal behaviour in combinational circuits when more than one input is changing simultaneously.
Expect that logic output is sampled with registers.

What's valid logic level in your design? Is 0.75 V valid high level?

 

[KlausST]

Hi,

me too sees the spikes as non critical and just normal...
In case you need to get rid of them ... just add a D-FF at each output.

What I´m more worried about is the different voltage levels of the "/Y" signal. It seems it is either floating or short circuited.

Klaus

 

[rayan_ee]

Hi Klaus,
I am also concerned about the different voltage levels, I checked the blocks individually and they seemed to work fine, but when implemented in the ALU circuit I am facing this issue. What could be causing this? any suggestion ? Thanks.

 

[dick_freebird]

Perhaps a gross lack of reasonable node capacitances
and maybe limiting output resistance on ideal models?

Timing skew between mux switches inter- and intra-
switch-cell?

 

[KlausST]

What could be causing this? any suggestion ? Thanks.

already answered!

Klaus

 

[andre_luis]

It is supposed that the output will be sampled at a clock with at least double frequency of the above signals, or any other one so that the output signal is read in a steady region quite after the transition; this is what a synchronous approach is expected to do.