Is anyone aware of a freely available library that enables easy parsing
and possibly modification of wiring and hieararchies in verilog code from
a script/program ? Any of the usual languages that are used on unix systems would be fine (perl, tcl, c, python...).
It is gone but i remember i can access it by way of some kind of web cache . I forgot the web-cache site name . Do anyone know the way to browser the obsolete web page ?