eternal_nan
Full Member level 3
tcl used with verilog
Hi All,
Is anyone aware of a freely available library that enables easy parsing
and possibly modification of wiring and hieararchies in verilog code from
a script/program ? Any of the usual languages that are used on unix systems would be fine (perl, tcl, c, python...).
Hi All,
Is anyone aware of a freely available library that enables easy parsing
and possibly modification of wiring and hieararchies in verilog code from
a script/program ? Any of the usual languages that are used on unix systems would be fine (perl, tcl, c, python...).