Perl applications in EDA

jimjim2k · Dec 7, 2004

perl for eda

Hi to all

AS I had promised in:

1. h**p://

I start to collect useful perl scripts on EDA here:

Please help to gain this topic

-------------------------------------------------------------------------------------
1. Spectre to hspice converion tool:

Code:

#!/usr/bin/perl
# Nelson Hu
# EE464H
# 08/07/03

#######################################################
# This program "Spectre2Hspice.pl" generates Hspice code from
#  Spectre netlist (si.inp)
#  The ouput of this program will then be able to run in Hspice
#  for timing analysis

#######################################################
# how to use this program:
# in the folder where si.inp is found, type
#    perl /home/projects/abraham/vlsi464/spicetest/FinalTOOLS/Spectre2Hspice.pl si.inp 3
# the number 3 at the end is the resolution for the timing analysis. it there is a longer delay, a larger number is used
# so that when running Hspice, the code will not fail.

#######################################################
# Input:
#  si.inp
#  a number for resolution.

#######################################################
# Output:
#  %CELLNAME%.sp

#######################################################
# Transition Time and Output Capacitance
# Hspice will use these two column to generate a matrix of timing analysis
#######################################################

#transition time
@a = qw *5ps 50ps 100ps 150ps 200ps 250ps 300ps*;
#capacitance
@b = qw *0ff 3.5ff 17.5ff 35ff 87.5ff 105ff 231ff*;

#before 07/19/03
#@a = qw *0 10.695ps 40.71ps 70.75ps 156.49ps 301.6ps 591.8ps*;
#@b = qw *0 2FF 8FF 20FF 50FF 100FF 200FF* ;

#seokjin suggested
#@a = qw *0.03ps 0.1ps 0.4ps 0.9ps 1.5ps 2.2ps 3ps*;
#@b = qw *0.00035pf 0.021pf 0.0385pf 0.084pf 0.147pf 0.231pf 0.3115pf*;

#######################################################
# get the file name (usually si.inp)
#######################################################
open LALA, "$ARGV[0]";
@line = <LALA>;
close LALA;

#######################################################
# get the second argument, the resolution
#######################################################
$hp = $ARGV[1];

#######################################################
# aquire the name of the cell from si.inp and use the
# name of the cell to create %CELLNAME%.sp
#######################################################
foreach (@line){
	if ($_ =~ /Design cell name:/){
		@temp = split / /,$_;
		$filename = $temp[$#temp];
		chomp $filename;}}

open HSPICE, ">$filename.sp";

#######################################################
# look for gate and number of input
# $OtherInput is either "gnd" or "vdd".
#    it specifies for multiple inputs to tie all to gnd or vdd
# $Inverted is either "T" or "F".
#    it tells the program that the gate is inverted
# this section needs to be added for new type of logic cells
#######################################################

$NumberOfInput = $filename;
if ($filename =~ /inv/){
    $NumberOfInput = 1;
    $output = "Z";
    $inverted = "T";}
elsif ($filename =~ /buf/){
    $NumberOfInput = 1;
    $output = "Z";
    $inverted = "F";}
elsif ($filename =~ /mux/){   #might not work
    $NumberOfInput = 3;
    $OtherInput = " vdd";
    $output = "Z";
    $inverted = "F";}
elsif ($filename =~ /nand/){
    $NumberOfInput =~ s/nand//g;
    $NumberOfInput =~ s/x[\d]+//g;
    $OtherInput = " vdd";
    $output = "Z";
    $inverted = "T";}
elsif ($filename =~ /nor/){
    $NumberOfInput =~ s/nor//g;
    $NumberOfInput =~ s/x[\d]+//g;
    $OtherInput = " gnd";
    $output = "Z";
    $inverted = "T";}
elsif ($filename =~ /xor/){
    $NumberOfInput =~ s/xor//g;
    $NumberOfInput =~ s/x[\d]+//g;
    $OtherInput = " gnd";
    $output = "Z";
    $inverted = "F";}
elsif ($filename =~ /and/){
    $NumberOfInput =~ s/and//g;
    $NumberOfInput =~ s/x[\d]+//g;
    $OtherInput = " vdd";
    $output = "Z";
    $inverted = "F";}
elsif ($filename =~ /or/){
    $NumberOfInput =~ s/or//g;
    $NumberOfInput =~ s/x[\d]+//g;
    $OtherInput = " gnd";
    $output = "Z";
    $inverted = "F";}

if ($NumberOfInput == 1){
    $input = "A";}
if ($NumberOfInput == 2){
    $input = "A B";}
if ($NumberOfInput == 3){
    $input = "A B C";}
if ($NumberOfInput == 4){
    $input = "A B C D";}
if ($NumberOfInput == 5){
    $input = "A B C D E";}

$inout = $input." ".$output;

#######################################################
# to replace the "\" and carriage return (if the line is too long)
# with carriage return and a "+" in HSPICE format
#######################################################
for ($n = 0; $n <= $#line; $n++){
	if ($line[$n] =~ /\\\n/){
		chomp $line[$n];
		chop $line[$n];
		$line[$n] .= $line[($n + 1)];
		$line[$n] =~ s/  //g;}
		}

#######################################################
# to discard all the lines except the one starts with
# _inst
#######################################################
$n = 0;
foreach (@line) {
	if ($_ =~ /_inst\d+/){
		$new[$n] = $_;
		$n++;}
		}
#######################################################
# replace _inst with C* or M* and take out the word
# capacitor and region=sat. also take out "(", ")", "!"
#######################################################
$M = 1; $C = 1;
foreach (@new) {
	if (($_ =~ /tsmc20P/) or ($_ =~ /tsmc20N/)){
		$_ =~ s/_inst[\d]+/M$M/g;
		$M++;}
	if ($_ =~ /capacitor/){
		$_ =~ s/_inst[\d]+/C$C/g;
		$C++;
		$_ =~ s/capacitor//g;}
	$_ =~ s/ region\=sat//g;
	$_ =~ s/\(//g;
	$_ =~ s/\)//g;
	$_ =~ s/\!//g;
	$_ =~ s/  / /g;}

#######################################################
# duplicate m if m is greater than 2
#######################################################

foreach (@new) {
	@values = split / /,$_;
	$values[$#values] =~ s/m=//g;
	$temp = $values[$#values];
	chomp $temp;
	$values[$#values] = "\n";
	$_ = join " ",@values;
	$temp--;
	$copy = $_;
	for (1..$temp) {
		$new[$#new + 1] = $copy;
		@change = split / /,$new[$#new];
		if ($change[0] =~ s/M[\d]+/M$M/g){;
		$M++;}
		if ($change[0] =~ s/C[\d]+/C$C/g){;
		$C++;}
		$new[$#new] = join " ",@change;
		}}

#######################################################
# exchange w,l; as,ad; ps,pd
#######################################################

foreach (@new) {
	@values = split / /,$_;
	if ($values[0] =~ /M(\d)/){
		($values[7], $values[6]) = ($values[6], $values[7]);
		($values[9], $values[8]) = ($values[8], $values[9]);
		($values[11], $values[10]) = ($values[10], $values[11]);}
	$_ = join " ",@values;}

#######################################################
# adding the beginning of the file
#######################################################

$middle = join " ",@new;
$middle =~ s/\n /\n/g;

$top_middle = "\*".$filename.".sp\n.options SPICE NOMOD AUTOSTOP LVLTIM=3\n.param ttra=0.1n LV=0.1e-12\n.temp 27\n\n.include \"/usr/local/packages/cadence/local/models/hspice/standalone/tsmc20P.m\"\n.include \"/usr/local/packages/cadence/local/models/hspice/standalone/tsmc20N.m\"\n.global vdd\n.global gnd\n\n\n.subckt $filename $inout\n". $middle.".ends\n";

#######################################################
# find number of input
#######################################################
@input = split / /,$input;
$n_input = $#input;		#number of input - 1
$G = " gnd";
$V = " vdd";
$I = " input";
$O = " output";

chomp $hp;
$period = $hp + $hp;
$wholeperiod = $period + $hp;
$resolution = (($period + 1) / 10000);

print "the resolution is ".$resolution."\n";

$lastpart = "X".$filename.$I.$OtherInput x $n_input.$O." ".$filename."\nCLOAD".$O.$G." LV\n\nVa".$I.$G." PULSE\(0,3.3,1p,Ttra,Ttra,".$hp."n,".$period."n\)\n\nvdd".$V.$G." 3.3\n\n";

#######################################################
# middie-last part
#######################################################
if ($inverted eq "T"){
    $abc = ".MEAS TRAN cell_rise TRIG V($I) val=1.65 TD=0n fall=1\n+\tTARG V($O) val=1.65 rise=1\n".
	   ".MEAS TRAN cell_fall TRIG V($I) val=1.65 TD=0n rise=1\n+\tTARG V($O) val=1.65 fall=1\n".
	   ".MEAS TRAN rise_slew TRIG V($O) val=0.33 TD=0n rise=1\n+\tTARG V($O) val=2.97 rise=1\n".
	   ".MEAS TRAN fall_slew TRIG V($O) val=2.97 TD=0n fall=1\n+\tTARG V($O) val=0.33 fall=1\n".
	   ".TRAN ".$resolution."N ".$wholeperiod."N sweep DATA=DATNM\n";}
elsif ($inverted eq "F"){
    $abc = ".MEAS TRAN cell_rise TRIG V($I) val=1.65 TD=0n rise=1\n+\tTARG V($O) val=1.65 rise=1\n".
	   ".MEAS TRAN cell_fall TRIG V($I) val=1.65 TD=0n fall=1\n+\tTARG V($O) val=1.65 fall=1\n".
	   ".MEAS TRAN rise_slew TRIG V($O) val=0.33 TD=0n rise=1\n+\tTARG V($O) val=2.97 rise=1\n".
	   ".MEAS TRAN fall_slew TRIG V($O) val=2.97 TD=0n fall=1\n+\tTARG V($O) val=0.33 fall=1\n".
	   ".TRAN ".$resolution."N ".$wholeperiod."N sweep DATA=DATNM\n";}

#######################################################
# vary capacitance and delay time
# change @a, @b on top
#######################################################
@c;
$#c = 0;
foreach $a (@a) {
	foreach $b (@b) {
		$c[$#c++] = ($a."\t".$b."\n");}}
$c = join " ",@c;
$c =~ s/\n /\n/g;

$datnm = ".DATA DATNM\nTtra\tLV\n$c.ENDDATA\n";

#print $datnm;

#######################################################
# change .alter
#######################################################
@last;
$count = 2;
for (1..$n_input){
	$last[0] = "X$filename";
	$last[1] = $OtherInput;
	for (1..$n_input){
		$last[$_ + 1] = $OtherInput;}
	$last[$count++] = $I;
	$last .= ".alter\n@last $O $filename\n";
	}
$last .= ".end\n";

#######################################################
# combine all
#######################################################

$final = "$top_middle"."\n"."$lastpart"."$abc\n"."$datnm"."\n"."$last";
print HSPICE $final;

close HSPICE;

-------------------------------------------------------------------------------------

jimjim2k · Dec 7, 2004

perl eda

-------------------------------------------------------------------------------------
2. Various EDA Formats conversions

Formats

blif2cnf
A BLIF to CNF translator. This script accepts one or more files in BLIF format and converts each one to CNF format (proposed for the 1993 DIMACS challenge on SAT).

iscas2cnf
An ISCAS'89 to CNF translator. This script accepts one or more files in ISCAS'89 format and converts each one to CNF format (proposed for the 1993 DIMACS challenge on SAT).

iscas2blif
An ISCAS'89 to BLIF translator. This script accepts one or more files in ISCAS'89 format and converts each one to BLIF format.

miter
Script for creating a MITER given two circuits described in ISCAS'89 format. This script is useful for equivalence checking purposes.

cnf2lp
Script for translating instances of SAT (in CNF format) into LP format (used by the linear programming solver lp-solve).
cnf2pbf
Script for translating instances of SAT (in CNF format) into PBF format (used by the BCP solver bsolo).
cnf2prime
Script for creating a BCP instance (in PBF format) for computing the minimum-size prime implicant of a Boolean function (in CNF format).
bcp2pbf
Script for translating instances of BCP (in the BCP format used by the BCP solver Scherzo) into PBF format (used by the BCP solver bsolo).
pbf2bcp
Script for translating instances of BCP in PBF ormat (used by the BCP solver bsolo) into BCP format (used by the BCP solver scherzo).
pbf2cnf
Script for translating instances of BCP in PBF format (used by the BCP solver bsolo) into CNF format.
pbf2lp
Script for translating instances of BCP in PBF format (used by the BCP solver bsolo) into LP format (used by the linear programming solver lp-solve).
pbf2opb
Script for translating instances of BCP in PBF format (used by the BCP solver bsolo) into OPB format (used by the pseudo boolean solver opbdp).

2.1. h**p://sat.inesc-id.pt/~jpms/scripts/

* -> t

tnx

-------------------------------------------------------------------------------------

jimjim2k · Dec 7, 2004

eda perl

-------------------------------------------------------------------------------------
3. Blif file into SPICE file

The Perl script can translate the blif file into SPICE file

3.1. h**p://www-unix.ecs.umass.edu/~kzhou/
3.2. h**p://www-unix.ecs.umass.edu/~kzhou/blif2spice.pl

* -> t

tnx

-------------------------------------------------------------------------------------

jimjim2k · Dec 7, 2004

verilog++

-------------------------------------------------------------------------------------

4. HDL2HTML

This PERL script takes an HDL file (VHDL or Verilog) and produces a HTML formatted version of it. It is handy for design reviews of your code - publish your design on your company's intranet, email etc... A byproduct of this utility is that since it is in HTML, it is not easily copied or compiled.

4.1. h**p://www.millogic.com/downloads.htm

* -> t

tnx

-------------------------------------------------------------------------------------

jimjim2k · Dec 7, 2004

perl coding for eda applications

-------------------------------------------------------------------------------------

5. Verilog-Perl

This library is intended as a building point for Verilog support in the Perl language.

5.1. h**p://www.veripool.com/verilog-perl.html
5.2. h**p://cpan.uwinnipeg.ca/htdocs/Verilog-Perl/

* -> t

tnx

-------------------------------------------------------------------------------------

jimjim2k · Dec 7, 2004

perl eda

-------------------------------------------------------------------------------------

6. ScriptSim

Seamless integration of Python, Perl, and Tk with your Verilog® simulations.

6.1. h**p://www.nelsim.com/

* -> t

tnx

-------------------------------------------------------------------------------------

jimjim2k · Dec 7, 2004

how to generate perl file from spice file

-------------------------------------------------------------------------------------

7. Verilog++ : a Verilog preprocessor

Verilog++ is a preprocessor for Verilog files that introduces two new constructs to Verilog: arbitrary code inclusion and parameterized module generation. These features give more flexibility than the VHDL 'generate' statement.

Verilog++ preprocesses its input files in two steps, using a programs called vvparse. During the first phase of the preprocessing, any code inclusions are executed. During the second phase of the preprocessing, parameterized modules are resolved and any source files containing the required parameterized module declarations are processed.

7.1. h**p://www.mpce.mq.edu.au/~spon/verilog/

* -> t

tnx

-------------------------------------------------------------------------------------

jimjim2k · Dec 7, 2004

opbdp 2007

-------------------------------------------------------------------------------------

8. The Verilog to html converter

The Rough Verilog Parser
If you write perl scripts to extract information from verilog files you might think that the parser that v2html uses to parse the verilog could be ripped out a used in your next script. Well it probably could - and I've tried to make it easy to do this by separating out the parser from the all the other stuff that v2html does. I called it 'The Rough Verilog Parser' and made it a perl module.

8.1. h**p://www.burbleland.com/v2html/rvp.html

* -> t

tnx

-------------------------------------------------------------------------------------

jimjim2k · Dec 7, 2004

vvparse

-------------------------------------------------------------------------------------

9. Verilog-Pli

Verilog:

li provides the ability to call Verilog PLI functions from Perl.

9.1. h**p://www.veripool.com/verilog-pli.html

* -> t

tnx

-------------------------------------------------------------------------------------

jimjim2k · Dec 7, 2004

top 10 eda application scripts

-------------------------------------------------------------------------------------

10. How to use Perl in your Verilog HDL Design Flow?

Anyone who designs with Verilog HDL has probably grown tired of generating module instantiations in a hierarchical design, or creating a new top level or lower level Verilog HDL module. I have generated a few Perl Scripts that will automatically generate the module instantiations, top level module, and lower level module for you. These Perl Scripts can be invoked from within VI/VIM/GVIM, or a DOS Command Window. If you invoke them from within VI, the script output will be printed in the current file. If you invoke them from within a DOS Command Window, then you will have to either cut and paste into your Verilog HDL file or pipe the output to a new file.

10.1 h**p://www.ece.ucdavis.edu/~jwwebb/using_perl_with_verilog.shtml

* -> t

tnx

-------------------------------------------------------------------------------------

jimjim2k · Dec 7, 2004

tsmc20p.m

-------------------------------------------------------------------------------------

11. ScriptEDA

This page is dedicated to linking scripting languages such as Perl,Python and Tcl to any freely available EDA tools.

11.1. h**p://www-cad.eecs.berkeley.edu/~pinhong/scriptEDA/

* -> t

tnx

-------------------------------------------------------------------------------------

jimjim2k · Dec 7, 2004

perl eda auto

-------------------------------------------------------------------------------------

12. Verilog Code Generator

The Verilog hardware description language
The Verilog Hardware Description Language (IEEE-1364) is a language intended to model hardware systems (in particular, but by no means exclusively, electronic integrated circuits).

The basic entity in a Verilog program (often call a netlist) is the module. A module can be compared to a subroutine or function, but a better analogy is to visualise every module as a small IC.

12.1 h**p://www.dcs.gla.ac.uk/~wim/verilog_codegen.shtml

* -> t

tnx

-------------------------------------------------------------------------------------

jigjack · Apr 14, 2005

perl split chomp eda

hi jimjim2k,

you have done a good help for Perl beginers like me.. thanks a lot.

can you suggest me where can i find a soft copy or e-book of "Mastering Perl/Tk" from O'Reilly.

please let me know ...
thanks once again ..

jimjim2k · Apr 15, 2005

.meas tran

jigjack said:
hi jimjim2k,

you have done a good help for Perl beginers like me.. thanks a lot.

can you suggest me where can i find a soft copy or e-book of "Mastering Perl/Tk" from O'Reilly.

please let me know ...
thanks once again ..

Hi
Online soft-copy:
Mastering Perl/Tk

1. h**p://files.printf.dk/docs/perl_bookshelf/tk/index.htm

* -> t

tnx

jigjack · Jun 14, 2005

perlå’Œeda

hi jimjim2k,

thanks for the reply... i found the perl/tk link sent by you to be very useful....

can you please tell me how can i interface parallel/serial port using PERL?

thanks

Anil Rana · Aug 27, 2005

blif nor

good job jimjim2k
keep it up

jimjim2k · Aug 28, 2005

hspiced perl

jigjack said:
hi jimjim2k,

thanks for the reply... i found the perl/tk link sent by you to be very useful....

can you please tell me how can i interface parallel/serial port using PERL?

thanks

Hi

You may search in the Perl programmer's paradise!!

1. h**p://search.cpan.org

2. h**p://search.cpan.org/~scott/Device-ParallelPort-1.00/lib/Device/ParallelPort.pm
3. h**p://search.cpan.org/~andrewho/Sys-PortIO-0.1/PortIO.pm

* -> t

tnx

ankit12345 · Apr 12, 2007

v2html gvim

Hey.............post abt the script which generated the cofegaration regester file in verilog from documentation.

Welcome to EDAboard.com

Perl applications in EDA

Advanced Member level 3

Advanced Member level 3

Advanced Member level 3

Advanced Member level 3

Advanced Member level 3

Advanced Member level 3

Advanced Member level 3

Advanced Member level 3

Advanced Member level 3

Advanced Member level 3

Advanced Member level 3

Advanced Member level 3

Member level 1

Advanced Member level 3

Member level 1

Junior Member level 1

Advanced Member level 3

Banned

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor