Performing STA on analog block

Hi,

I have a doubt regarding performing timing analysis for an analog module in a design. I am new to STA and I have read in some blogs that STA does not deal with analog blocks. Please help me regarding this on how my approach should be to perform STA on analog blocks.

Thanks in advance!

Hi Pavan,
Yes, STA cant be done on analog blocks but STA can be done when analog blocks are instantiated in digital blocks.
You need to do spice simulations for analog blocks to get the timing information for them. This timing info can be saved as .lib and this .lib can be read at top level to get the interface timing info.

Hi Deepu,

If I want to perform to check how the input and output pins of this analog block are constrained, how should I proceed?

first, you should know if your block is clock less or not.
I means if the inputs are only configurations coming from digital side, then there is not setup&hold constraints. You must modelisze with set_load, the input of the analog block to have the correct driver cell.
and for the outputs, that's the same idea with set_drive_cell, to indicate the equivalent drivers used the analog block, and then your digital design could estimate the correct driver.
You need to exchange some infos with your analog designer.

if your analog module is clocked, and the i/o is relative to this clock, then you could add set_[max¦min]_delay, and then during the Pnr/STA, this constraint will be checked.

To build a "fastest" liberty model, you could used the quick time model in Primetime.

Hi rca,
Thank you. This block has two clocks. One at the input side and other at the output side. Do you mean to say that the inputs should be constrained with input clock and output should be constrained with output clock?

yes, if the i/o are related to these clock.

There may be some skew requirements too for inputs to the analog block, especially if the analog block does not have a clock input to it. These inputs should come from the digital block surrounding the analog block. You may model these using "data-to-data checks" in STA (these constraints might well be defined in .lib or you may need to explicitly define these checks using sdc constraints). A data to data check constrains a data signal wrt to another data signal. I found one article on the web https://vlsiuniverse.blogspot.in/2013/07/data-to-data-checks-constraining.html that provides good explanation for these checks.

skew is more related to clock network "quality".

Not only clock network quality, but also for critical bus signals that should arrive at the interface simultaneously.