Peak FT of a CMOS Transistor

cmos ft measure

How does one find the Peak FT of a CMOS transistor and the associated current say in common source using something like ADS or Spectre ?

ft of cmos

the definition of the ft is
the frequency where the current gain
drops to 1.
So you have to connect the drain to a constant voltage and connect the gate voltage to a constant voltage that will providing appropriate bias condition to the device (it should operate in saturation and resonable drain current.). Then you have to run
ac simulation and find the current transfer function
Iout/Iin, Iin ac current from the gate bias dc voltage source, Iout is the ac current of the drain bias dc voltage (or ac drain current). The frequency where this ratio pass through 1 is ft.
Of course this value will change with respect to biasing condition, i.e. Vgs-Vt (together with w/l and Idrain), you will have different ft values

ft definition cmos

i am looking to create an LNA in CMOS and was told to bias the transistor at peak ft current density.

is that true by the way -- does that give minimum NF ?

thanks for the help.

what does ft peak mean transistor

in amplifier design guide of @DS u can plot the FT curves and then extarct the paek

how to find peak ft

hmmm...no foundry characterizes the MOSFET upto a frequency even close to the fT offered by the technology....as the measurement instrument must surely be able to measure uptil several tenths of gigahertz...its damn costly right?

example: for a 0.18µm CMOS, my foundry has characterized the MOSFET only uptil 20GHz and I am sure that the fT is surely far above 20GHz.

so what does this mean?

it means that any form of analysis or any circuit "centric" simulator trick, if u please, will not yield correct predictions as the model is itself valid only till 20GHz or what ever!!!

Still I did cook up a circuit which I used to plot the AC current gain thing from 1GHz to 100GHz for fun

So I am showing the circuit....I have run an AC analysis by driving the grounded common-source MOSFET with an ideal current source whose "AC" magnitude was set to 1 so that a direct plot of iout in dB will indicate the fT hopefully and the result was disastrous as predicted....it did not show the correct fT I think

I am sure that the fT of a 0.18µm tech is surely not above 100GHz!!!

I wonder if someone will kindly please confirm my testing method please?

measure circuit ft transistor cmos

this technique (biasing for lowest NF at peak FT) means you take the peak of the FT, which is much lower than FT itself..

you take the peak of the FT, which is much lower than FT itself..

Click to expand...

I don't understand what you are trying to say here.

I wouldn't recommend biasing your mosfet at peak Ft. One of the dominant parameters affecting NF is the gate resistance. Therefore, to reduce the series resistance of the gate, you would have to size your transistor to a very large transistor. If you run that transistor at peak Ft, then you will consume a lot of power, which is not desired for hand held applications. Therefore you will have to run your transistor at lower than peak Ft. Since the gm is inversely proportional to Ft, you will have optimize for Idrain for NF and bandwidth.

I would recommend running a Fmin vs. Idrain simulation on the mosfet you want to use. From the simulation results, you can pick the optimal Idrain for low Fmin.

in most submicron processes the point for peak ft is NEAR the NFMIN point to 1st order.

that is what i have seen at least.